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Old exams in TSEA26

For most of these exams I have included a solution proposal. I've tried to solve each exercise in a fairly realistic fashion. That is, even if the exam allows you to solve an exercise in a fairly non-efficient manner (e.g. by using a very long critical path), I've tried to avoid such "unrealistic" solutions here. (Or I might provide two alternative solutions, one "simple" and one realistic.) It is my hope that you might be able to learn a new trick or two by studying these solution proposals. (But don't worry if you wouldn't come up with these tricks yourself on the exam, there are usually many other ways to solve most of these exercises.) Also, note that many of these exam problems has been cleaned up and moved into the exercise collection that you will use during the tutorials.

Exam FAQ

How should I annotate a schematic? (Updated Oct 2015)

It is important that for example the width of all signals in the schematic (or RTL code for that matter) can be inferred. One option is of course to annotate the bit width of all signals. However, this will quickly become rather cumbersome. The following figure contains some guidelines on how to handle annotations without cluttering the schematic too much:

Can I use Verilog or VHDL on the exam? (Updated Oct 2015)

Yes. You may, if you want to, use Verilog or VHDL instead of drawing a schematic. However, in this course we only trust the synthesis tool to create hardware which is identical to what you have actually described in your RTL code. For example, if you want hardware multiplexing, you need to design your hardware yourself such that this is possible.

Rationale

Outside of this course you can typically trust the synthesis to do a decent job of optimizing the hardware. However, one of the goals of this course is to ensure that you have the microarchitectural knowledge to do this yourself. This will in turn allow you to design RTL code that is easy for the synthesis tool to optimize (for example by using hardware multiplexing), and if necessary perform such hardware optimizations yourself if the synthesis tool turns out to be unable to do so. Therefore I consider it important that you show the ability to perform such optimizations yourself.

On the other hand, since the course is not about the design of arithmetic components such as adders and multipliers, we assume that the synthesis tool is able to create optimized arithmetic operators. (If you are interested in learning about this part of the digital design flow you are encouraged to participate in the computer arithmetic course instead.)

Examples

The following is a bad example in this course since it contains two adders/subtracters rather than only one: 
always @(posedge clk) begin : ALU
    case(Ca)
        0: result = A + B;
        1: result = A - B;
        2: result = A ^ B;
        3: result = A | B;
    endcase
end
Whereas the following code is a good example since hardware multiplexing is explicitly implemented here: 
reg carry_in;
always @* begin
    if(Cb) begin
        carry_in = 1;
        op_b = B;
    end else begin
        carry_in = 0;
        op_b = ~B;  // (Note that ~ is use for bitwise inversion in Verilog and not the !-operator)
    end
end

always @(posedge clk) begin
    case(Cc)
        0: result = A + op_b + carry_in;
        1: result = A ^ B;
        2: result = A | B;
    endcase
end
Similarly, the following is a bad example since it use a relatively costly component (e.g. magnitude comparation): 
  always @* begin : SAT
      result = opa[31:16];
      if(opa < 40'hff80000000) begin
          result = 16'h8000;
      end else if(opa > 40'h007fffffff) begin
          result = 16'h7fff;
      end
  end
The following is instead a good example since it shows that you know that the operation above reduces to simple bit comparators rather than the more costly magnitude comparation. 
  always @* begin : SAT
      result = opa[31:16];
      if((opa[39:31] != 9'h1ff) || (opa[39:31] != 9'h000)) begin
          if(opa[39]) begin
              result = 16'h8000;
          end else begin
              result = 16'h7fff;
          end
      end
  end
Personally, I prefer a combination of HDL and schematics because both approaches have their specific strengths and weaknesses.

How important is the syntax? Can I write some sort of pseudo HDL code?

The correct syntax is not very important as long as the meaning is clear. I will not deduct points because you have forgotten a semicolon as long as the meaning is clear. However, if you are not sure of the syntax it is a good idea to comment your code so that the meaning is clear.

A very common situation where syntax (or an explanation of what you actually intended) is very important is the case of the replication operator in Verilog: 

  •  5'b11111 == {5{1'b1}} // Correct attempt at replicating a bit five times
  •  5'b11111 != 5'b1 // Incorrect attempt at replicating a bit five times
This usually comes up in saturation handling as in the following example: 
// Correct 12 -> 8 bit saturation:
always @* begin
    if (in[11:7] == 5'b11111) begin
        out[7:0] = in[7:0];
    end else if(in[11:7] == 5'b0) begin
        out[7:0] = in[7:0];
    end else begin
        out[7:0] = { in[11], ~{7 {in[11]}}};
    end
end
// Also correct:
always @* begin
    if (in[11:7] == {5{1'b1}}) begin
        out[7:0] = in[7:0];
    end else if(in[11:7] == 5'b0) begin
        out[7:0] = in[7:0];
    end else begin
        out[7:0] = { in[11], ~{7 {in[11]}}};
    end
end
// NOT CORRECT
always @* begin
    if (in[11:7] == 5'b1) begin // <-- BUG!
        out[7:0] = in[7:0];
    end else if(in[11:7] == 5'b0) begin
        out[7:0] = in[7:0];
    end else begin
        out[7:0] = { in[11], ~{7 {in[11]}} };
    end
end
For the last alternative I would be forced to deduct points because I will not be able to decide whether the bug is caused by a lack of knowledge regarding Verilog syntax (which wouldn't be a big deal on this exam) or a lack of knowledge regarding saturation (which would be a big deal). Note that a comment that shows your intention here would save the day (e.g. "// Compare in[11:7] with five ones").

Clocked structures in HDL

Another detail that you need to be careful about is clocking. I have noticed that many students that use VHDL or Verilog on the exam forget to indicate that a clock is used for registers and flip-flops. So if you want to create a clocked structure (such as a flag register in an ALU) please make sure that you actually indicate that a clock is used (for example by using an always @(posedge clk) statement.

I failed the exams with only three points. Could you give me a few points so I can pass?

Short answer: No (except in those cases where there is a clear mistake made by the person who corrected the exam, such as when the person who corrected the exam forgot to correct a question).

Long answer: Whenever a student receives a score which is just below a grade boundary I can assure you that I will look very carefully at the exam to see whether there is any way that I can pass the student. This will take into account not only individual questions but the entire exam taken as a whole to ascertain whether the student has demonstrated enough knowledge of the subject matter to be allowed to pass. Unfortunately it sometimes happen that I don't have any choice but to confirm a score which is just below the limit for passing. (As a side note, this usually works to your advantage as few teachers look carefully at an exam that is a few points above a particular grade boundary.)

I didn't pass the exam, can you give me some extra assignment instead?

I don't allow this for the following reasons:
  • It is expected that we will treat all students fairly. However, if we do allow some sort of extra assignment it will be be hard to say where the line should be drawn between when to allow such an assignment and when to disallow it. It is also hard to design an extra assignment in such a way that it will fairly allow the student to demonstrate that they have learned all material relevant to the course.
  • We already give the exam three times per year in order to give students a second (or third) chance to demonstrate that they know the contents of the course.
  • Creating a high quality extra assignment and correcting it is going to consume resources which we would rather use on improving the course in ways such that all students can benefit from it.
  • Finally, during a written examination we have special measures in place to ascertain that the students are not able to cooperate with each other. In other words, a written examination will examine the knowledge of each student on an individual basis. If I would hand out an extra assignment it would be much harder for me to guarantee this.

References

Note that this list has been inspired by the reasoning contained in a policy document from EIE: Policy gällande examination, komplettering och sk "plussning" av tentamensresultat i samband med skriftlig tentamen.

I didn't pass the exam, can you give me an extra written exam?

Probably not. We already have three exams per year to make sure that students have a fair chance of passing the course. Normally it will take around two to three days for me to prepare an examination, and I don't think it is fair that I should spend so much time just for one student instead of spending that time on improving the course.

However, I might entertain this idea if there are extraordinary circumstances, such as:

  • This is the only course that you have left
  • You have finished your master's thesis
  • You need your diploma to be able to apply for a job (typically only relevant for prospective Ph.D. students)
  • The next regular exam will not be given for a long time
  • I believe that you will have a good chance of passing the exam (e.g., you got close to a passing grade on the latest exam)
  • I am not too busy with other teaching or research

Note that such an extraordinary exam might look quite different from the regular exams as the regular exams are intended to be relatively easy to correct in a fair manner. On the other hand, for an extraordinary exam it will be more efficient for me to spend little time on the creation of the exam while spending a longer time correcting it.

In other words, don't waste both my and your time if your strategy to such an extraordinary exam would be to briefly study old exams and hoping that I will base such an exam upon existing exams and merely change the wording of a question.

I can't come to the exam since I will not be in Linköping (or Sweden), can I do the exam somewhere else?

While technically possible, it is very rare that the department allows this (when I looked into this some time ago it had only happened once during the last five years or so). Note that we already have three exams per year in order to handle situations where a student for some reason is unable to attend a certain exam.

For more information, see the FAQ for examinations at LiTH. (Not translated into English, but Google Translate will do an adequate job on this page.)

I will not be in Linköping for a significant amount of time, how do I handle any questions I may have regarding the correction of the exam?

I can probably scan your exam and email it to you, especially if you are only a 2-3 points below a grade boundary.

TSEA26 - Design of Embedded DSP Processors

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Page responsible: Oscar Gustafsson
Last updated: 2018-11-15