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TSIU03 - System Design

NOTE!! These pages are outdated. The course pages are now in Lisam.


  • 2022-09-13: Due to really heavy workload at the moment, the deadline for Assignment 3 is delayed one week. If required, we may delay more deadlines.
  • 2022-09-13: Project launged. All groups have had their first supervisor meeting. You should now have access to Muxen 4.
  • 2022-07-04: If you are eager to learn about FPGA's, you can have a look att www.youtube.com/watch?v=CfmlsDW3Z4c.
  • 2022-07-04: This page starts to be updated for 2022. Parts marked with "(2021)" are not yet updated. Those are likely to change. Also the updated page may change.

About TSIU03

Course Description

TSIU03 is an introductory course to circuit design using VHDL. The general description of the course can be found in the syllabus.

The course is intended for bachelor students with no previous knowledge in VHDL. Students are however supposed to have previous knowledge in switching theory and it is highly recommended to have studied circuit design before.

Master students (specially those that have knowledge in circuit design and programming skills) should preferably apply for the more advanced course Design of Digital Systems (TSTE12). Due to a partial overlap between the content in TSIU03 and TSTE12, it is only allowed to register for one of these courses.

Registration for the course: Lisam. Deadline for registration: 2022-09-12 08:00.


The course includes methods and tools for the design and implementation of electronic systems using VLSI techologies. The design methods aim at reducing the design time and guarantee correct designs as well as ensuring that performance requirements are met.

Course Content

Design of complex systems, project organization, planning and documentation. ♦ Problem capture, specification, system design, complexity, partitioning and validation. ♦ Use of CAD-CAE tools. ♦ Behavioral description using VHDL. ♦ System architectures. ♦ Automatic synthesis of logic and implementation using FPGA technologies.

Course Web Page and Course Folder

Course Web Page: www.isy.liu.se/en/edu/kurs/TSIU03/.

Course Folder: K:\TSIU03\. (applicable in the lab)


You can see a map of rooms and offices here.


The course consists of a series of lectures, laboratories, home assignments and a project.

Specifically, the course includes:

  • 10 lectures (2 hours each).
  • 4 labs (4 to 8 hours each, plus some spare sessions).
  • 3 home assignments.
  • 1 project (running during the entire course in different phases).

The course has 8 ECTS:

  • 3 ECTS correspond to LAB1 (the labs).
  • 5 ECTS correspond to PRA1 (the assignments and project).

Evaluation: Grades are given as "pass" or "fail".

3 ECTS are for the labs, which corresponds to 80 hours. The scheduled time for labs is 30 hours. The lectures are divided between LAB1 and PRA1, but say 14 hours of lectures are for LAB1. Hence, you are supposed to spend about 36 hours of unscheduled time for the labs.

5 ECTS are for PRA1 (projects and assignments), which is 133 hours. The assignments are assumed to take roughly 15 hours. The remaining lecture time is 6 hours. Hence, you are supposed to spend about 112 h per student in the project.

Course Books

"VHDL for Logic Synthesis", Andrew Rushton. John Wiley & Sons, 2011 (3rd edition). ISBN-13: 978-0470688472. Links: LIU Library, Online Version.

"Digital Design: An Embedded Systems Approach Using VHDL", Peter J. Ashenden. Morgan Kaufmann, 2007. ISBN-13: 978-0123695284. Links: LIU Library, Online Version.

Note: You might need to be within the univerisy network in order to access those.

The students can have access to the books in different ways:

  • The LIU library has bought two printed copies of each book that the students can borrow.
  • The books are available online for all the students from the web page of the LIU library with unlimited access.
  • Thus, it is not needed to buy the books. Only if you like any of them and want to get a printed copy for the future, you can buy it. The books can be purchased at Bokad (in Kårallen).

Page responsible: Petter Källström
Last updated: 2023-05-12