Department of Electrical Engineering

Project TSTE12

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The project will be carried out in larger groups of students (4-6 people/group). The groups are defined through random selection by the examiner.

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A project specification can be found below.

Notes on how the report should look like and how the presentation is to be carried out is available here .

Deadlines for Y, D and ED students 2023:

1st group meeting: Friday 1 Sept. (ok to have meeting on Monday 4/9)
Initial requirement specification: Tuesday 5 Sept.
lab1, required for contiuation of project: Wednesday 6 Sept.
Final requirement specification: Friday 8 Sept.
Initial project plan and design specification: Tuesday 12 Sept.
Final project plan and design specification: Friday 15 Sept.
Final presentation and report: Friday 20 Okt.

Deadlines for all other students 2023:

1st group meeting: Friday 7 Sept.
Initial requirement specification: Tuesday 12 Sept.
lab1, required for contiuation of project: Wednesday 13 Sept.
Final requirement specification: Friday 15 Sept.
Initial project plan and design specification: Tuesday 19 Sept.
Final project plan and design specification: Friday 22 Sept.
Final presentation and report: Friday 27 Oct.


Templates for the requirement specification and the group meetings will be available at /courses/TSTE12/material/projekt/LIPS-templates/.

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FLASH image programming

The FLASH can be programmed so it contains predefined data, for example a background image. The programming can be performed by following this sequence:

0. Load the TSTE12 module and start a mentorskal. All commands below are given in this window.

1. Make sure you have a binary file containing the data you want to store in the FLASH. That is, no HEX, S-record or other format should be used for this file.

2. Translate the binary file into a supported S-record file using

  /opt/altera/quartus/17.1.1/nios2eds/bin/bin2flash --input=inputfilename --output=newflashfilename --location=0
  

The --location parameter defines where in the FLASH memory the data should be stored. Change this if you want the data to be stored at a start address different from 0.

3. Make sure the FPGA is restarted with the default design loaded (dA scrolling on the 7-segment display). If not, powercycle the board.

4. Put the image into the FLASH. This requires knowledge about the FPGA programming device.Give the command

  jtagconfig
  

to find out which board is connected, and what the -c parameter should be. Use the following to copy the contents of the file created in step 2 above into the FLASH:

  nios2-flash-programmer --base 0 -c "USB-Blaster on southfork-11 [USB 5.1]" newflashfilename
  

FLASH programming can only change a '1' into a '0'. Changing a '0' to '1' can only be done by first erasing the contents of the FLASH, followed by programming of the FLASH. Erasing the contents of the FLASH can be done using

  nios2-flash-programmer --base 0 -c "USB-Blaster on southfork-11 [USB 5.1]" --erase-all

  

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Group definitions

Group definition can be found HERE!
NOTE: This list may change once the deadline for completing lab 1 has passed.

Supervisors

Group 1,2:
Cheolyong Bae Cheolyong.Bae@liu.se
Group 3,4:
Olov Andersson Olov.Andersson@liu.se
Group 5,6,7:
Kent Palmkvist kent.palmkvist@liu.se

File name	Size	Last Modification Time
Participants-tste12-2023_230919.pdf	29K	19 September 2023 11:31
ProjectSpecification_2022.pdf	59K	26 August 2022 13:35
Report_and_presentation_notes.pdf	25K	13 October 2023 10:49