Department of Electrical Engineering

Laborations TSTE12

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The lab hours are intended for practice using the tools, practice writing small VHDL programs, and also completing three lab tasks. It is suggested that the tutorial (see the course material page) is completed first before solving the lab tasks.

The first task is to decode an attached keyboard (standard PC). This laboration is also an introduction to the graphical entry tool HDL Designer which will be used in the project. Synthesis and programming of hardware (FPGA) is also included. The hardware documentation is available on the computer system at /courses/TSTE12/material/DE2-115_SystemCD_v3.0.6/

Notes to laboration number one is available below. Please note that the computer tools have been upgraded and there may be minor differences in the notes compared to the current computer system.

NOTE: To get a pass on the first lab shall the testbench model indicate what tests have been done, and the outcome of those, using a text output. The simulation shall also stop by itself once all tests have been carried out. It should be enough for the user to enter "run -all" in the simulator.

Task number 2 consists of using an image present in the SRAM memory, and display this image on an attached VGA screen. Notes on the second task is available below (480 kB pdf). Please note that the computer tools have been upgraded and there may be minor differences in the notes compared to the current computer system.

The third lab task is not necessary for students of the Y, D and ED programs. The task is to implement the ability to modify the image in the SRAM based on microcoded structure. A pre-defined structure is available that only needs its microprogram to be defined.

The notes describing the microprogramming lab is found below (88 KB pdf). Please note that the computer tools have been upgraded and there may be minor differences in the notes compared to the current computer system.

NOTE: A small clarification of the lab notes section 3 "Copy of template design":
After completing step 3, the lab3_microprog library must be opened by double click on the name in the project tab of the design manager. This is necessary to create the directory and open it in the design manager.
In step 4 must all components and blocks be selected, but not the library itself (TSTE12_lab3_DE2_115).

The altera_mf library is required to simulate the top level of the lab 3 setup. To simulate without the altera_mf library, do the simulation of the subblock instead (to not include the PLL desing).

NOTE: The following description does not currently work!
The full design can be simulated if the altera_mf library is added by following the notes in Adding Altera downstream libraries found below. Please note that any simulation that includes the PLL will be very timeconsuming, and may require changing the default time step in Modelsim to be set to 10 ps or smaller.

Lab 1 must be completed no later than 11 September 2024 at 21.00 for Y, D and ED students in order to be allowed to participate in the project. The corresponding deadline for all other students is 18 September 2024 at 21.00. No lab results will be examined for the Y, D and ED students between 19 September and 22 October 2024, and for all other students the same restriction applies between 26 September and 21 October 2024. This time should instead be used for the project task.

File name	Size	Last Modification Time
Adding_Altera_downstream_libraries.pdf	331K	08 October 2019 14:23
TSTE12_Lab1_240902.pdf	176K	02 September 2024 22:48
TSTE12_Lab2_240911.pdf	470K	11 September 2024 18:13
TSTE12_Lab3_191008.pdf	84K	08 October 2019 08:27