Department of Electrical Engineering

Course materiel TSTE12

Some material additional material may be found in the Lisam course room at liuonline.sharepoint.com/sites/Lisam_TSTE12_2023HT_NF.

The tutorial below is supposed to be carried out first. This will give you some experience of how to use the tools. You need to know how to use the tools both for the lab, project and handin tasks.

The exercises from the book consists mainly of exercises on the VHDL language. These exercises should be carried out in "pure" VHDL in Modelsim, without the use of HDL Designer (the tool used in the Laborations).

Complete the tutorial first (found below) before solving any of the exercises from the book. Note that the excerices are only suggestions, and you are not expected complete every single one of them.

Suitable exercises (taken from the course book "VHDL for Engineers"):
Chapter 2: 8-30
Chapter 3: 6-31
Chapter 4: 2-36
Chapter 5: 1-28
Chapter 6: 4-11,13-18,20-22
Chapter 7: 8-15
Chapter 8: 4,6,14-22,36-42
Chapter 9: 2-31
Chapter 10: 4-9,13-33
Chapter 12: 2-3,6-7,9-14
Chapter 13: 1-4

Alternative exercises can be found at e.g., www.altera.com (look for Support->Training,University program->Student->Tutorials)

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Tutorial

Chapter #	Contents
1	Introduction, VHDL design example
2	Modelsim compilation and simulation
3	HDLdesigner, textual and graphic entry

File name	Size	Last Modification Time
Tutorial_200826.pdf	2.9M	30 August 2020 13:11