Reducing emissions of the key greenhouse gas methane (CH4) is increasingly highlighted as being important to mitigate climate change. Effective emission reductions require cost-effective ways to measure CH4 to detect sources and verify that mitigation efforts work. We present here a novel approach to measure methane at atmospheric concentrations by means of a low-cost electronic nose strategy where the readings of a few sensors are combined, leading to errors down to 33 ppb and coefficients of determination, R-2, up to 0.91 for in situ measurements. Data from methane, temperature, humidity, and atmospheric pressure sensors were used in customized machine learning models to account for environmental cross-effects and quantify methane in the ppm-ppb range both in indoor and outdoor conditions. The electronic nose strategy was confirmed to be versatile with improved accuracy when more reference data were supplied to the quantification model. Our results pave the way toward the use of networks of low-cost sensor systems for the monitoring of greenhouse gases.

This paper describes the development and testing of a simple local seasonal forecast system of rainfall and hydrological conditions. The primary target group is agricultural extension officers who communicate forecasts to small-scale farmers at local level. Two pilot areas within the Limpopo river basin in South Africa were used, one in the Luvuvhu river basin in Vhembe district and the other in the Letaba river basin in Mopani district. Local rainfall and hydrological forecasts of runoff, soil moisture and evapotranspiration were produced, built on readily available deterministic seasonal meteorological forecasts for large-scale rainfall from CSIR (Council for Scientific and Industrial Research, South Africa), produced from an ensemble of seasonal forecasts using the CCAM (Conformal-Cubic Atmospheric Model) global forecast model. Hydrological forecasts were produced through a "proxy" approach, whereby outputs from the ACRU (Agricultural Catchment Research Unit) agrohydrological model provided expected hydrological responses from observed years that are representative of the rainfall anomalies predicted by the global seasonal forecast. Locally monitored soil moisture augmented the hydrological forecasts. The local seasonal forecast system does not require sophisticated calculations or a complex operational environment and complements coarser scale forecasts disseminated by the provincial departments of agriculture. Results of three rainfall seasons from 2013 to 2016 in the pilot areas showed the proxy approach to have relatively good matches between forecasts and available observations, showing better predictability for below normal rainfall seasons with exception for an extreme monthly rainfall event. The forecasts matched observed conditions best during the strong El Nin similar to o phase of ENSO (El Nin similar to o Southern Oscillation) for 2015/2016.

In this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 2(2ENOB), whereas the speed-bound increases by 2(ENOB-2) and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2(ENOB-1). The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, f(s)/2.

Purpose: Spatial resolution for current scintillator-based computed tomography (CT) detectors is limited by the pixel size of about 1 mm. Direct conversion photon-counting detector prototypes with silicon- or cadmium-based detector materials have lately demonstrated spatial resolution equivalent to about 0.3 mm. We propose a development of the deep silicon photon-counting detector which will enable a resolution of 1 ?? µ m , a substantial improvement compared to the state of the art. Approach: With the deep silicon sensor, it is possible to integrate CMOS electronics and reduce the pixel size at the same time as significant on-sensor data processing capability is introduced. A Gaussian curve can then be fitted to the charge cloud created in each interaction.We evaluate the feasibility of measuring the charge cloud shape of Compton interactions for deep silicon to increase the spatial resolution. By combining a Monte Carlo photon simulation with a charge transport model, we study the charge cloud distributions and induced currents as functions of the interaction position. For a simulated deep silicon detector with a pixel size of 12 ?? µ m , we present a method for estimating the interaction position. Results: Using estimations for electronic noise and a lowest threshold of 0.88 keV, we obtain a spatial resolution equivalent to 1.37 ?? µ m in the direction parallel to the silicon wafer and 78.28 ?? µ m in the direction orthogonal to the wafer. Conclusions: We have presented a simulation study of a deep silicon detector with a pixel size of 12 × 500 ?? µ m 2 and a method to estimate the x-ray interaction position with ultra-high resolution. Higher spatial resolution can in general be important to detect smaller details in the image. The very high spatial resolution in one dimension could be a path to a practical implementation of phase contrast imaging in CT.

Body area networks (BANs), cloud computing, and machine learning are platforms that can potentially enable advanced healthcare outside the hospital. By applying distributed sensors and drug delivery devices on/in our body and connecting to such communication and decision-making technology, a system for remote diagnostics and therapy is achieved with additional autoregulation capabilities. Challenges with such autarchic on-body healthcare schemes relate to integrity and safety, and interfacing and transduction of electronic signals into biochemical signals, and vice versa. Here, we report a BAN, comprising flexible on-body organic bioelectronic sensors and actuators utilizing two parallel pathways for communication and decision-making. Data, recorded from strain sensors detecting body motion, are both securely transferred to the cloud for machine learning and improved decision-making, and sent through the body using a secure body-coupled communication protocol to auto-actuate delivery of neurotransmitters, all within seconds. We conclude that both highly stable and accurate sensing-from multiple sensors-are needed to enable robust decision making and limit the frequency of retraining. The holistic platform resembles the self-regulatory properties of the nervous system, i.e., the ability to sense, communicate, decide, and react accordingly, thus operating as a digital nervous system.

A CMOS sensor chip was used, together with an Arduino microcontroller, to create and verify a low-power low-cost optical motion detector for use in traffic detection under dark and daylight conditions. The chip can sense object features with very high dynamic range. On-chip near sensor image processing was used to reduce the data to be transferred to a host computer. A method using local extrema point detection was used to estimate motion through time-to-impact (TTI). Sensor data from the headlights of an approaching/passing car were used to extract TTI values similar to estimations from distance and speed of the object. The method can be used for detection of approaching objects to switch on streetlights (dark conditions) or sensors for traffic lights instead of magnetic sensors in the streets or conventional cameras (dark and daylight conditions). A sensor with a microcontroller operating at low clock frequency will consume less than 30 mW in this application. 

Limited application and use of forecast information restrict smallholder farmers ability to deal with drought in proactive ways. This paper explores the barriers that impede use and uptake of seasonal climate forecasts (SCF) in two pilot communities in Limpopo Province. Current interpretation, translation and mediation of national SCF to the local context is weak. A local early warning system (EWS) was developed that incorporated hydrological modelled information based on national SCF, locally monitored rainfall and soil moisture by a wireless sensor network, and signs from indigenous climate indicators. We assessed to what degree this local EWS could improve interpretation of SCF and increase understanding and uptake by farmers. Local extension staff and champion farmers were found to play important knowledge brokering roles that could be strengthened to increase trust of SCF. The local EWS provided added value to national SCF by involving community members in local monitoring, enacting knowledge interplay with indigenous knowledge and simplifying and tailoring SCF and hydrological information to the local context. It also helped farmers mentally prepare for upcoming conditions even if many do not currently have the adaptive mindsets, economic resources or pre-conditions to positively respond to SCF information.

As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radios digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into todays digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital EA modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

Linearity and efficiency are important parameters in determining the performance of any wireless transmitter. Pulse-width modulation (PWM) based transmitters offer high efficiency but suffer from low linearity due to image and aliasing distortions. Although the problem of linearity can be addressed by using an aliasing-free PWM (AF-PWM), these transmitters have a lower efficiency as they can only use linear power amplifiers (PAs). Moreover, an all-digital implementation of such transmitters is not possible. The aliasing-compensated PWM transmitter (AC-PWMT) has a higher efficiency due to the use of switch-mode PAs (SMPAs) but uses outphasing to eliminate image and aliasing distortions and requires a larger silicon area. In this study, the authors propose a novel transmitter that eliminates both aliasing and image distortions while using a single SMPA. The transmitter can be implemented using all-digital techniques and achieves a higher efficiency as compared to both AF-PWM and AC-PWM based transmitters. Measurement results show an improvement of 11.3, 7.2, and 4.3 dBc in the ACLR as compared to the carrier-based PWM transmitter (C-PWMT), AF-PWMT, and AC-PWMT, respectively. The efficiency of the proposed transmitter is similar to that of C-PWMT, which is an improvement of 5% over AF-PWMT.

This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18m CMOS process and the chip measures 3mm(2). Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11V while maintaining an output voltage of 1.8V at an output power of 16.2W. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4.

This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

This paper explores the barriers that limit the use of SFs by smallholder farmers and policy-makers and practical, political and personal changes in the Limpopo Department of Agriculture and Rural Development (LDARD) that could enhance greater usage of SFs in risk management. Interviews and workshops were performed with LDARD staff at province, district municipality and service center level within the Extension and Advisory Services and Disaster Management Services divisions. Many extension officers repeatedly pointed out the need to move from reactive to proactive policies. This could entail creating effective channels for bottom-up communication of emerging ground conditions coupled with relief and support efforts distributed even during hazardous events, not only after greater losses have been felt. Different perceptions and understandings of if and how SFs inform national subsidies and site-specific recommendations distributed in the province to extension staff that departmental communication could be improved to increase trust and reliability of the forecasts and accompanying recommendations for farmers.

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 mu A, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 my. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8 x 11.5 mu m(2). (C) 2016 Elsevier B.V. All rights reserved.

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition, a secondary-bit approach to dynamically shift decision levels for error correction is employed. To reduce the power consumption, the ADC also features a power-optimized comparator with bias control. Prototyped in a 65-nm CMOS process, the ADC consumes 1.98 mu W and provides an effective number of bit (ENOB) of 12.5 b at 0.8 V while occupying an active area of 0.28 mm(2).

Organic electronics have been developed according to an orthodox doctrine advocating "all-printed, "all-organic and "ultra-low-cost primarily targeting various e-paper applications. In order to harvest from the great opportunities afforded with organic electronics potentially operating as communication and sensor outposts within existing and future complex communication infrastructures, high-quality computing and communication protocols must be integrated with the organic electronics. Here, we debate and scrutinize the twinning of the signal-processing capability of traditional integrated silicon chips with organic electronics and sensors, and to use our body as a natural local network with our bare hand as the browser of the physical world. The resulting platform provides a body network, i.e., a personalized web, composed of e-label sensors, bioelectronics, and mobile devices that together make it possible to monitor and record both our ambience and health-status parameters, supported by the ubiquitous mobile network and the resources of the "cloud".

This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm².

This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 x 16 DPS with pixel size of 23 x 23 mu m(2) and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images. (C) 2015 Elsevier B.V. All rights reserved.

This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ΔΣ DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1–1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ΔΣ DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ΔΣ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

Channel mismatches in time-interleaved analog-to-digital converters (TIADCs) typically result in significant degradation of the ADCs dynamic performance. Offset, gain, and timing mismatches have been widely investigated whereas nonlinearity mismatches have not. In this work, we analyze the influence of nonlinearity mismatches by using a polynomial model. As a cost measure we use the signal-to-noise and distortion ratio (SNDR) and then derive a compact formula describing the dependency on nonlinearity mismatches. Based on the spectral characteristics of the TIADCs, we propose a foreground estimation method and a compensation method using a cascaded structure of adders and multipliers. Through behavioral-level simulations, we prove the validity of the derivations and demonstrate that the proposed estimation and compensation method can bring a considerable amount of improvement in the combined TIADCs dynamic performance. The proposed method is efficient assuming that a smooth approximation of the nonlinearity mismatches is sufficient.

Measured propagation loss for capacitive body-coupled communication (BCC) channel (1 MHz to 60 MHz) is limitedly available in the literature for distances longer than 50 cm. This is either because of experimental complexity to isolate the earth-ground or design complexity in realizing a reliable communication link to assess the performance limitations of capacitive BCC channel. Therefore, an alternate efficient full-wave electromagnetic (EM) simulation approach is presented to realistically analyze capacitive BCC, that is, the interaction of capacitive coupler, the human body, and the environment all together. The presented simulation approach is first evaluated for numerical/human body variation uncertainties and then validated with measurement results from literature, followed by the analysis of capacitive BCC channel for twenty different scenarios. The simulation results show that the vertical coupler configuration is less susceptible to physiological variations of underlying tissues compared to the horizontal coupler configuration. The propagation loss is less for arm positions when they are not touching the torso region irrespective of the communication distance. The propagation loss has also been explained for complex scenarios formed by the ground-plane and the material structures (metals or dielectrics) with the human body. The estimated propagation loss has been used to investigate the link-budget requirement for designing capacitive BCC system in CMOS sub-micron technologies.

In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P_{1 dB} > +5 dBm over frequency range of 0.5-3 GHz.

Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.

Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.

This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.

This paper introduces two polynomial finite-length impulse response (FIR) digital filter structures with simultaneously variable fractional delay (VFD) and phase shift (VPS). The structures are reconfigurable (adaptable) online without redesign and do not exhibit transients when the VFD and VPS parameters are altered. The structures can be viewed as generalizations of VFD structures in the sense that they offer a VPS in addition to the regular VFD. The overall filters are composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. A systematic design algorithm, based on iteratively reweighted l(1)- norm minimization, is proposed. It generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails. The paper considers two different structures, referred to as the basic structure and common-subfilters structure, and compares these proposals as well as the existing cascaded VFD and VPS structures, in terms of arithmetic complexity, delay, memory cost, and transients. In general, the common-subfilters structure is superior when all of these aspects are taken into account. Further, the paper shows and exemplifies that the VFDPS filters under consideration can be used for simultaneous resampling and frequency shift of signals.

This paper proposes optimal finite-length impulse response (FIR) digital filters, in the least-squares (LS) sense, for compensation of chromatic dispersion (CD) in digital coherent optical receivers. The proposed filters are based on the convex minimization of the energy of the complex error between the frequency responses of the actual CD compensation filter and the ideal CD compensation filter. The paper utilizes the fact that pulse shaping filters limit the effective bandwidth of the signal. Then, the filter design for CD compensation needs to be performed over a smaller frequency range, as compared to the whole frequency band in the existing CD compensation methods. By means of design examples, we show that our proposed optimal LS FIR CD compensation filters outperform the existing filters in terms of performance, implementation complexity, and delay.

The paper proposes an optimization technique for the design of variable digital filters with simultaneously tunable bandedge and fractional delay using a fast filter bank (FFB) approach. In the FFB approach, full band signals are split into multibands, and each band is multiplied by a proper phase shift to realize the variable fractional delay. In the proposed technique, in the formulation of the optimization of the 0th stage prototype filter of the FFB, the ripples of the filters in the subsequent stages are all taken into consideration. In addition, a shaping filter is applied to the last retained band of the FFB to form the transition band of the variable filter, such that the transition width of each band in the FFB can be relaxed to reduce the computational complexity. In total three shaping filters, constructed from a prototype filter, can be shared by different bands, so that the extra cost incurred due to the shaping filter is low.

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the capacitor array imperfections. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The analysis shows the DAC performance is determined by the clock feed-through and settling effects in the SC array and not by the capacitor mismatch or kT/C noise, which appear negligible in this application. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. The high linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete Nyquist-rate DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜ_ΑΑ. The first variant ΔΣΜ_ΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜ_pp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜ_ΑΑ, ΔΣΜ_ΑP and ΔΣΜ_pp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜ_pp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

An ultra-low power wake-up radio receiver using no oscillators is described. The radio utilizes an envelope detector followed by a baseband amplifier and is fabricated in a 130-nm complementary metal-oxide-semiconductor process. The receiver is preceded by a passive radio-frequency voltage transformer, also providing 50 Ω antenna matching, fabricated as transmission lines on the FR4 chip carrier. A sensitivity of -47 dBm with 200 kb/s on-off keying modulation is measured at a current consumption of 2.3 μ A from a 1 V supply. No trimming is used. The receiver accepts a -13 dBm continuous wave blocking signal, or modulated blockers 6 dB below the sensitivity limit, with no loss of sensitivity.

This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

We propose a non-binary stochastic decoding algorithm for low-density parity-check (LDPC) codes over GF(q) with degree two variable nodes, called Adaptive Multiset Stochastic Algorithm (AMSA). The algorithm uses multisets, an extension of sets that allows multiple occurrences of an element, to represent probability mass functions that simplifies the structure of the variable nodes. The run-time complexity of one decoding cycle using AMSA is O(q) for conventional memory architectures, and O(1) if a custom memory architecture is used. Two fully-parallel AMSA decoders are implemented on FPGA for two (192,96) (2,4)-regular codes over GF(64) and GF(256), both achieving a maximum clock frequency of 108 MHz. The GF(64) decoder has a coded throughput of 65 Mb/s at E-b/N-0 = 2.4 dB when using conventional memory, while a decoder using the custom memory version can achieve 698 Mb/s at the same E-b/N-0. At a frame error rate (FER) of 2 x 10(-6) the GF(64) version of the algorithm is only 0.04 dB away from the floating-point SPA performance, and for the GF(256) code the difference is 0.2 dB. To the best of our knowledge, this is the first fully parallel non-binary LDPC decoder over GF(256) reported in the literature.

To investigate the epidemiology of upper extremity injuries in male elite football players and to describe their characteristics, incidence and lay-off times. less thanbrgreater than less thanbrgreater thanBetween 2001 and 2011, 57 male European elite football teams (2,914 players and 6,215 player seasons) were followed prospectively. Time-loss injuries and exposure to training and matches were recorded on individual basis. less thanbrgreater than less thanbrgreater thanIn total, 11,750 injuries were recorded, 355 (3 %) of those affected the upper extremities giving an incidence of 0.23 injuries/1,000 h of football. The incidence in match play was almost 7 times higher than in training (0.83 vs. 0.12 injuries/1,000 h, rate ratio 6.7, 95 % confidence interval 5.5-8.3). As much as 32 % of traumatic match injuries occurred as a result of foul play situations. Goalkeepers had a significantly higher incidence of upper extremity injuries compared to outfield players (0.80 vs. 0.16 injuries/1,000 h, rate ratio 5.0, 95 % confidence interval 4.0-6.2). The average absence due to an upper extremity injury was 23 +/- A 34 days. less thanbrgreater than less thanbrgreater thanUpper extremity injuries are uncommon among male elite football players. Goalkeepers, however, are prone to upper extremity injury, with a five times higher incidence compared to outfield players. less thanbrgreater than less thanbrgreater thanII.

The effect of temperature variation on pulse height determination accuracy is determined for a photon counting multibin silicon detector developed for spectral CT. Theoretical predictions of the temperature coefficient of the gain and offset are similar to values derived from synchrotron radiation measurements in a temperature controlled environment. By means of statistical modeling, we conclude that temperature changes affect all channels equally and with separate effects on gain and threshold offset. The combined effect of a 1 degrees C temperature increase is to decrease the detected energy by 0.1 keV for events depositing 30 keV. For the electronic noise, no statistically significant temperature effect was discernible in the data set, although theory predicts a weak dependence. The method is applicable to all x-ray detectors operating in pulse mode.

We investigated the energy resolution of a segmented silicon strip detector for photon-counting spectral computed tomography (CT). The detector response to different monochromatic photon energies and various photon fluxes was characterized at the Elettra synchrotron. An RMS energy resolution of 1.50 keV has been demonstrated for 22 keV photons at zero flux, and it deteriorated as a function of input count rate at a rate of 5.1 eV mm(2)/Mcps. The charge sharing effect has been evaluated. The results show that around 11.1% of the interacting photons experience charge sharing for 22 keV photons and 15.3% for 30 keV.

Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 mu m CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.

This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient because most of the overall arithmetic complexity is due to the HB filter which is common to all Farrow-structure subfilters. This paper extends and generalizes existing results. Firstly, frequency-response masking (FRM) HB filters are utilized which offer further complexity reductions. Secondly, both linear-phase and low-delay subfilters are treated and combined which offers trade-offs between the complexity, delay, and magnitude response overshoot which is typical for low-delay filters. Thirdly, the HB filter is replaced by a general filter which enables additional frequency-response constraints in the upper frequency band which normally is treated as a dont-care band. Wide-band design examples (90, 95, and 98% of the Nyquist band) reveal arithmetic complexity savings between some 20 and 85% compared with other structures, including infinite-length impulse response structures. Hence, the VFD filter structures proposed in this paper exhibit the lowest arithmetic complexity among all hitherto published VFD filter structures.

A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7-point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.

This paper deals with time-varying finite-length impulse response (FIR) filters used for reconstruction of two-periodic nonuniformly sampled signals. The complexity of such reconstructorsincreases as their bandwidth approaches the whole Nyquist band. Reconstructor design that yields minimum reconstructor order requires expensive online redesign while those methods that simplify online redesign result in higher reconstructor complexity. This paper utilizes a two-rate approach to derive a single-rate structure where part of the complexity of the reconstructor is moved to a symmetric filter so as to reduce the number of multipliers. The symmetric filter is designed such that it can be used for all time-skew errors within a certain range, thereby reducing the number of coefficients that need online redesign. The basic two-rate based reconstructor is further extended to completely remove the need for online redesign at the cost of a slight increase in the total number of multipliers.

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This brief considers fractional-delay finite-length impulse response (FIR) filters and a class of supersymmetric Mth-band linear-phase FIR filters utilizing partially symmetric and partially antisymmetric impulse responses. Design examples reveal significant multiplication savings, depending on the specification, as compared to traditional filters.

This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. less thanbrgreater than less thanbrgreater thanModel and predistortion performance are evaluated on a 32-dBm peak-output-power class-D outphasing PA in CMOS with on-chip transformers. The excitation signal is a 5-MHz downlink WCDMA signal with peak-to-average power ratio of 9.5 dB. Using the proposed digital predistorter, the 5-MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 to -45.6 dBc. The 10-MHz ACLR was improved by 6.4 dB, from -44.3 to -50.7 dBc, making the amplifier pass the 3GPP ACLR requirements.

This paper introduces multimode transmultiplexers (TMUXs) in which the Farrow structure realizes the polyphase components of general lowpass interpolation/decimation filters. As various lowpass filters are obtained by one set of common Farrow subfilters, only one offline filter design enables us to cover different integer sampling rate conversion (SRC) ratios. A model of general rational SRC is also constructed where the same fixed subfilters perform rational SRC. These two SRC schemes are then used to construct multimode TMUXs. Efficient implementation structures are introduced and different filter design techniques such as minimax and least-squares (LS) are discussed. By means of simulation results, it is shown that the performance of the transmultiplexer (TMUX) depends on the ripples of the filters. With the error vector magnitude (EVM) as the performance metric, the LS method has a superiority over the minimax approach.

We describe a high-rate energy-resolving photon-counting ASIC aimed for spectral computed tomography. The chip has 160 channels and 8 energy bins per channel. It demonstrates a noise level of ENC= electrons at 5 pF input load at a power consumption of andlt;5mW/channel. Maximum count rate is 17 Mcps at a peak time of 40 ns, made possible through a new filter reset scheme, and maximum read-out frame rate is 37 kframe/s.

This correspondence introduces efficient realizations of wide-band LTI systems. They are single-rate realizations but derived via multirate techniques and sparse bandpass filters. The realizations target mid-band systems with narrow don’t-care bands near the zero and Nyquist frequencies. Design examples for fractional-order differentiators demonstrate substantial complexity savings as compared to the conventional minimax-optimal direct-form realizations.

This correspondence outlines a method for designing two-stage Nyquist filters. The Nyquist filter is split into two equal and linear-phase finite-length impulse response spectral factors. The per-time-unit multiplicative complexity, of the overall structure, is included as the objective function. Examples are then provided where Nyquist filters are designed so as to minimize the multiplicative complexity subject to the constraints on the overall Nyquist filter. In comparison to the single-stage case, the two-stage realization reduces the multiplicative complexity by an average of 48%. For two-stage sampling rate conversion (SRC), the correspondence shows that it is better to have a larger SRC ratio in the first stage. © 2006 IEEE.

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm².

This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

This paper introduces a class of wide-band linear-phase finite-length impulse response (FIR) differentiators. It is based on two-rate and frequency-response masking techniques. It is shown how to use these techniques to obtain all four types of linear-phase FIR differentiators. Design examples demonstrate that differentiators in this class can achieve substantial savings in arithmetic complexity in comparison with conventional direct-form linear-phase FIR differentiators. The savings achievable depend on the bandwidth and increase with increasing bandwidth beyond the break-even points which are in the neighborhood of 90% (80%) of the whole bandwidth for Type II and III (Type I and IV) differentiators. The price to pay for the savings is a moderate increase in the delay and number of delay elements. Further, in terms of structural arithmetic operations, the proposed filters are comparable to filters based on piecewise-polynomial impulse responses. The advantage of the proposed filters is that they can be implemented using non-recursive structures as opposed to the polynomial-based filters which are implemented with recursive structures.

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This paper introduces reconfigurable nonuniform transmultiplexers (TMUXs) based on fixed uniform modulated filter banks (FBs). The TMUXs use parallel processing where polyphase components, of any user, are processed by a number of synthesis FB and analysis FB branches. One branch represents one granularity band, and any user can occupy integer multiples of a granularity band. The proposed TMUX also requires adjustable commutators so that any user occupies any portion of the frequency spectrum. The location and width of this portion can be modified without additional arithmetic complexity or filter redesign. This paper considers both cosine modulated and modified discrete Fourier transform FBs. It discusses the filter design, TMUX realization, and the parameter selection. It is shown that one can indeed decrease the arithmetic complexity by proper choice of system parameters. For the critically sampled case and if the number of channels is higher than necessary, we can reduce the arithmetic complexity. In case of an oversampled system, the arithmetic complexity can be reduced by proper choice of the number of channels and the roll-off factor of the prototype filter. The proposed TMUX is compared to existing reconfigurable TMUXs, and examples are provided for illustration.

A class of Farrow-structure-based reconfigurable bandpass finite-length impulse response (FIR) filters for integer sampling rate conversion is introduced. The converters are realized in terms of a number of fixed linear-phase FIR subfilters and two sets of reconfigurable multipliers that determine the passband location and conversion factor, respectively. Both Mth-band and general FIR filters can be realized, and the filters work equally well for any integer factor and passband location. Design examples are included demonstrating their efficiency compared to modulated regular filters. In addition, in contrast to regular filters, the proposed ones have considerably fewer filter coefficients that need to be determined in the filter design process.

The pad pitch of modern RF ICs is in order of few tens of micrometers. Connecting the large number of high speed I/Os to outside world with good signal fidelity and low cost is extremely challenging. To cope with this requirement, we need reflection-free transmission lines from on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow to wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that impedance variation is less then 3Ω for 50Ω microstrip when the width changes from 165μm to 940μm and substrate thickness changes from 100μm to 500μm. The Sparameter measurement on same microstrip shows S11 better then -9dB for the frequency range 1-6GHz.

A simulation technique is developed in TCAD to study the non-linear behavior of RF power transistor. The technique is based on semiconductor transport equations to swot up the overall non-linearity’s occurring in RF power transistor. Computational load-pull simulation technique (CLP) developed in our group, is further extended to study the non-linear effects inside the transistor structure by conventional two-tone RF signals, and initial simulations were done in time domain. The technique is helpful to detect, understand the phenomena and its mechanism which can be resolved and improve the transistor performance. By this technique, the third order intermodulation distortion (IMD₃) was observed at different power levels. The technique was successfully implemented on a laterally-diffused field effect transistor (LDMOS). The value of IMD₃ obtained is −22 dBc at 1-dB compression point (P _{1 dB}) while at 10 dB back off the value increases to −36 dBc. Simulation results were experimentally verified by fabricating a power amplifier with the similar LDMOS transistor.

A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.

This article presents a Monte Carlo simulation of the detector energy response in the presence of pileup in a segmented silicon microstrip detector designed for high flux spectral computed tomography with sub-millimeter pixel size. Currents induced on the collection electrode of a pixel segment are explicitly modeled and signals emanating from events in neighboring pixels are superimposed together with electronic noise before the entire pulse train is processed by a model of the readout electronics to obtain the detector energy response function. The article shows how the lower threshold and the time constant of the electronic filters need to be set in order to minimize the detrimental influence of cross talk from neighboring pixel segments, an issue that is aggravated by the sub-millimeter pixel size and the proposed segmented detector design.

Key blocker requirements of software defined radio receivers are identified from first principles. Three challenges are derived from these requirements, the need for passive filter banks or tunable passive filters, a very highly linear RF front-end and a high performance analog-to-digital converter. Each of these challenges is analyzed regarding possible solutions in the context of state-of-the art technology.

This article compares the performance of two different GaN transistor technologies, GaN HEMT on silicon substrate (PA1) and GaN on SiC (PA2), utilized in two broadband power amplifiers operating at 0.7 to 1.8 GHz. The study explores the broadband power amplifier potential of both GaN HEMT technologies for phased-array radar (PAR) and electronic warfare (EW) systems. The measured maximum output power for PA1 is 42.5 dBm (18 W) with a maximum PAE of 66 percent and a gain of 19.5 dB. The measured maximum output power for PA2 is 40 dBm with a PAE of 37 percent and a power gain slightly above 10 dB. The high power gain, ME, wider bandwidth and unconditional stability was obtained without feedback for the amplifier based on GaN HEMT technology, fabricated on Si substrate.

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed finite-length impulse response (FIR) filter structures. In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required. The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90 nm CMOS process.

Multiplication by constants can be efficiently realized using shifts, additions, and subtractions. In this work we consider how to select a fixed-point value for a real valued, rational, or floating-point coefficient to obtain a low-complexity realization. It is shown that the process, denoted addition aware quantization, often can determine coefficients that has as low complexity as the rounded value, but with a smaller approximation error by searching among coefficients with a longer wordlength.

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.

This paper presents a design approach for flexible RF circuits using Programmable Microwave Function Array (PROMFA) cells. The concept is based on an array of generic cells that can be dynamically reconfigured. Therefore, the same circuit can be used for various functions e.g. amplifier, tunable filter and tunable oscillator. For proof of concept a test chip has been implemented in 90nm CMOS process. The chip measurement results indicate that a single unit cell amplifier has a typical gain of 4dB with noise figure of 2.65dB at 1.5GHz. The measured input referred 1dB compression point is -8dBm with an IIP3 of +1.1dBm at 1GHz. In a single unit cell oscillator configuration, the oscillator can achieve a wide tuning range of 600MHz to 1.8GHz. The measured phase noise is -94dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 1.2GHz. A single unit cell oscillator consumes 18mW at 1.2GHz while providing -8dBm power into 50Ω load. In a single unit cell filter configuration, the tunable band pass filter can achieve a reasonable tuning range of 600MHz to 1.2GHz with a typical power consumption of 13mW at 1GHz. A single unit cell has a total chip area of 0.091mm2 including the coupling capacitors.

A very important limitation of high-speed analog-todigital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and todays designs.

In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter-the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay. © 2008 IEEE.

This paper introduces a least-squares filter design technique for the compensation of frequency response mismatch errors in M-channel time-interleaved analog-to-digital converters. The overall compensation system is designed by determining M filter impulse responses analytically through M separate matrix inversions. The proposed technique offers an alternative to least-squares techniques that determine all filters simultaneously. Several design examples are included for illustration.

This paper introduces a multimode transmultiplexer (TMUX) structure capable of generating a large set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow-based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design beforehand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow-based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system.

This paper proposes polynomial impulse response finite-impulse response filters for reconstruction of two-periodic nonuniformly sampled signals. The foremost advantages of using these reconstruction filters are that on-line filter design thereby is avoided and subfilters with fixed dedicated multipliers can be employed in an implementation. The overall implementation cost can in this way be reduced substantially in applications where the sampling pattern changes from time to time. The paper presents two different design techniques that yield optimum filters in the least-squares and minimax senses, respectively. Design examples are included that illustrate the benefits of the proposed filters. © 2007 IEEE.

This paper offers two main contributions to the theory of low-delay frequency-response masking (FRM) finite impulse response (FIR) filters. First, a thorough investigation of the low-delay FRM FIR filters and their subfilters or three different structures, referred to as narrow-, wide-, and middle-band filter structures, is given. The investigation includes discussions on delay distribution over the subfilters as well as estimation of the optimal periodicity of the periodic model filter. Second, systematic design procedures are given, with explicit formulas for distribution of the ripples and the delay to the subfilters. For each of the three structures, two design procedures are given that include joint optimization of the subfilters. The first proposal uses partly linear-phase FIR subfilters and partly low-delay FIR subfilters. Thus, it has a lower arithmetic complexity compared to the second proposal, which has exclusively low-delay FIR subfilters. The second proposal is instead more flexible and can handle a broader range of specifications. The design procedures result in low-delay FIR filters with a lower arithmetic complexity compared to previous results, for specifications with low delay and narrow transition band. © Birkhauser Boston 2007.

A crucial issue in the next-generation satellite-based communication systems is the satellite on-board reallocation of information which requires digital flexible frequency-band reallocation (FBR) networks. This paper introduces a new class of flexible FBR networks based on variable oversampled complex-modulated filter banks (FBs). The new class can outperform the previously existing ones when all the aspects flexibility, low complexity and inherent parallelism, near-perfect frequency-band reallocation, and simplicity are considered simultaneously.

This paper deals with reconstruction of nonuniformly sampledbandlimited continuous-time signals using time-varyingdiscrete-time finite-length impulse response (FIR) filters. Themain theme of the paper is to show how a slight oversamplingshould be utilized for designing the reconstruction filters in aproper manner. Based on a time-frequency function, it is shownthat the reconstruction problem can be posed as one that resemblesan ordinary filter design problem, both for deterministic signalsand random processes. From this fact, an analytic least-squaredesign technique is then derived. Furthermore, for an importantspecial case, corresponding to periodic nonuniform sampling, it isshown that the reconstruction problem alternatively can be posedas a filter bank design problem, thus with requirements on adistortion transfer function and a number of aliasing transferfunctions. This eases the design and offers alternative practicaldesign methods as discussed in the paper. Several design examplesare included that illustrate the benefits of the proposed designtechniques over previously existing techniques.

Multiple constant multiplication (MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. By utilizing redundancy between the coefficients the number of adders and subtracters is reduced resulting in a low complexity implementation. However, for digit-serial arithmetic a shift requires a flip-flop, and, hence, the number of shifts should be taken into consideration as well. In this work we investigate the area, speed, power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. We also introduce an algorithm for reducing both the number of adders and subtracters as well as the number of shifts.

Data representations for LDPC decoders using the sum-product algorithm in the log-likelihood domain are considered. It is suggested that the look-up table implementation of the domain transform function is separated into two parts, allowing a compact representation of the internal state data. Memories and bus widths can be reduced by typically 16\%, while the imposed hardware overhead is insignificant.

An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Muller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.

Drain noise current was measured at an extended temperature range on n-MOS transistors of various lengths made in a 0.18 urn process. A comparison with theoretical noise models strongly indicates the mechanism of shot noise produced near the source by diffusion currents, as proposed by Obrecht et al. © IEE 2005.

An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is −26 and −34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.

The problem of selecting codewords for memoryless low-power bus coding is considered. A graph-based procedure is proposed to obtain a subset of all possible codewords with minimum average energy consumption. The procedure can be applied to arbitrary cost models.

"nedslag från en tankeväckande resa på Öland. Vilka funderingar kan kopplas ihop med de platser som författarna besöker under resans gång? Vi får följa de naturvetenskapliga såväl som filosofiska tankar som uppstår längs resans väg."

This textbook provides a complete introduction to analog filters for senior undergraduate and graduate students. It covers the synthesis of analog filters as well as many other filter types including passive filters and filters with distributed elements. The material also addresses the basic circuit elements for the filters. Each chapter contains examples as well as problems and the author also provides a list of MATLAB functions.

Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability.  This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide.

Covering everything from signal processing algorithms to integrated circuit design, this complete guide to digital front-end is invaluable for professional engineers and researchers in the fields of signal processing, wireless communication and circuit design. Showing how theory is translated into practical technology, it covers all the relevant standards and gives readers the ideal design methodology to manage a rapidly increasing range of applications. Step-by-step information for designing practical systems is provided, with a systematic presentation of theory, principles, algorithms, standards and implementation. Design trade-offs are also included, as are practical implementation examples from real-world systems. A broad range of topics is covered, including digital pre-distortion (DPD), digital up-conversion (DUC), digital down-conversion (DDC) and DC-offset calibration. Other important areas discussed are peak-to-average power ratio (PAPR) reduction, crest factor reduction (CFR), pulse-shaping, image rejection, digital mixing, delay/gain/imbalance compensation, error correction, noise-shaping, numerical controlled oscillator (NCO) and various diversity methods.

  "Radio Design in Nanometer Technologies" addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. To that end, the book contains three parts: Part 1 is a general part discussing current and future wireless networks, chipset evolution over the past decade and ending with a discussion on radio requirements for software defined radio(SDR). Part 2 will focus on the digital baseband of a wireless chip set, flexible DSP cores for multi-standard wireless platforms and system-on-chip SoC implementation and design flow issues. Part 3 will be devoted to radio design issues starting at the transceiver level and going down to discuss critical issues facing design of future multi band multi standard radios for emerging wireless standards such as UMTS, WiMaX, MIMO and WLAN in a way that is consistent with the prevailing vision of SDR. As such, the book is the first volume that looks at the integrated radio design problem as a 'piece of a big puzzle', namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today's increasingly complex wireless systems

In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

Extending the wireless power transfer range in miniaturized remotely powered micro-devices is a big challenge due to the very small effective area and low gain of the mm-sized antenna utilized in the micro-devices, which limits the harvested RF energy. This paper presents a method for increasing the separation distance between an external energy source antenna as a transmitter (TX) and micro device antenna as a receiver (RX) beyond 10 cm by utilizing various TX antennas, including a conventional loop antenna, multiple patch antennas, and a rectangular cavity antenna, and a 2-turn double-sided square loop RX antenna, sized 1.2mm x 1.2mm on FR4 substrate, which can be mounted on top of a CMOS SoC. The performance of the wireless power transfer system is evaluated and compared in different scenarios. At the 434 MHz ISM band, the results indicate that the highest peak power transfer efficiency of -20 dB and the highest harvested DC voltage of 4 V through an 8-stage Dickson RF-DC converter are obtained inside the rectangular hollow cavity sized 49.6cm x 49.6cm x 30.4cm, as TX, with an input TX power of 20 dBm. Furthermore, the multiple patch antennas have a power transfer efficiency of -39 dB and a harvested DC voltage of 2.5 V at a distance of 10 cm with an input TX power of 37 dBm. The specific absorption rate of both cases stays below the limits established by IEEE.

Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE.

This paper proposes a dynamic range (DR) extension technique based on a two-step conversion for high-sensitivity multi-element pseudo-resistive (MEPR) transimpedance amplifiers (TIA). In optical biomedical sensors targeted for fluorescence measurement applications, the front-ends high sensitivity and wide DR are critical for accurately recording cellular variations. In this work, the most significant bits (MSB) are extracted by a 2-bit current digital-to-analog converter (DAC) then the least significant bits (LSB) are extracted by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The current DACs are composed of identical pseudo-resistor (PR) elements used in the TIA feedback to make the MSB extraction robust against the process and mismatch variations. This technique preserves the linearity of the conversion while using the current DACs to improve the DR. The proposed front-end implemented in 65 nm CMOS technology achieves a DR of 72.3 dB with current detection of 1 pA up to 4.13 nA at a sampling rate of 1 kS/s. The total front-end consumes a power of 45 mu w from a 2.5 V supply.

A digital switching scheme to reduce glitches and induce code-dependent randomization in digital-to-analog converters (DACs) is presented. The switching scheme is capable of generating a thermometer-like decoded bit sequence from a butterfly network. Due to the reduced switching activity, it mitigates the impact of timing issues, making it suitable for highspeed operation. From behavioral model simulations with a 10-bit current-steering DAC, a linearity improvement in spurious-free dynamic range of about 4 dBc is obtained for 10% amplitude mismatch in the current sources, demonstrating the improvement in linearity without the use of pseudo-random control signals.

Modern high data rate communication use modulated signals with large peak-to-average power ratios (PAPR). The power efficiency of such signals when using common types of power amplifiers (PAs) can be rather low, as they require a large output back-off (OBO) to be reasonably linear. In this paper, a recent new architecture for improving the efficiency at OBO, the load modulated balanced amplifier (LMBA), is studied by circuit and EM simulations for realization in a 180 nm CMOS process, including matching networks and power combiners (90 degrees couplers). The selected structure is a Doherty-like LMBA, where the control signal for the load modulation is generated by a separate, integrated amplifier. Simulated with on-chip inductor losses and center frequency of 2 GHz, the peak PAE at full output power (24 dBm) is 34.8%. At 6 dB OBO, the LMBA gives a PAE of 32.6% compared to 23.2% for a reference amplifier without load modulation, and load optimized for peak PAE, an absolute PAE improvement of 7.4% or a relative PAE improvement of 31.9%. The main limitation of the integrated CMOS LMBA appears to be losses in the passive components needed for matching and load modulation.

This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

One of the existing prototype detector systems for full-field photon-counting CT is a silicon detector developed by our group. Spatial resolution is clinically important to resolve small details and can enable more efficient phase-contrast imaging. However, improving the resolution is difficult as decreasing the pixel size is associated with technical challenges. By integrating CMOS electronics into the silicon sensor, it is possible to reduce the pixel size drastically while also introducing on-sensor data processing capabilities. In this work, we evaluate the feasibility of measuring the charge cloud shape of Compton interactions in a silicon strip detector to increase the spatial resolution. With an incident spectrum of 140 kVp, Compton interactions constitute 66.2% of the detected interactions. By combining a Monte Carlo photon simulation with a charge transport model, we study the charge cloud distributions and induced currents as functions of the interaction position. For a simulated silicon strip detector with a pixel size of 12x500 mu m(2), we present a method in which the interaction position can be determined. For an ideal case without electronic noise an average absolute error of 0.65 mu m is obtained in the direction along the wafer and 13.08 mu m in the trans-wafer direction. With simulated electronic noise and a lowest threshold of 0.88 keV the corresponding values are 1.38 mu m and 122.83 mu m. Our results show that the proposed method has the potential to very significantly increase the spatial resolution in a full-field photon-counting detector for CT.

Photon-counting silicon strip detectors are attracting interest for use in next generation CT scanners. For silicon detectors, a low noise floor is necessary to obtain a good dose efficiency. A low noise floor can be achieved by having a filter with a long shaping time in the readout electronics. This also increases the pulse length, resulting in a long deadtime and thereby a degraded count-rate performance. However, as the flux typically varies greatly during a CT scan, a high count-rate capability is not required for all projection lines. It would therefore be desirable to use more than one shaping time within a single scan. To evaluate the potential benefit of using more than one shaping time, it is of interest to characterize the relation between the shaping time, the noise, and the resulting pulse shape. In this work we present noise and pulse shape measurements on a photon-counting detector with two different shaping times along with a complementary simulation model of the readout electronics. We show that increasing the shaping time from 28.1 ns to 39.4 ns decreases the noise and increases the signal-to-noise ratio (SNR) with 6.5% at low count rates and we also present pulse shapes for each shaping time as measured at a synchrotron source. Our results demonstrate that the shaping time plays an important role in optimizing the dose efficiency in a photon-counting x-ray detector.

All-digital implementations of PWM-based wireless transmitters are gaining popularity. Unlike baseband PWM, RF-PWM has relaxed filtering requirements and is preferred due to a smaller chip size. This paper is aimed to highlight the differences between polar and quadrature implementations of RF-PWM-based transmitters. Using mathematical models and simulations, performance of the two implementations is compared. The mathematical analysis indicates that the quadrature implementation is expected to have higher quantization noise compared to the polar because of the shorter duty cycles at maximum amplitude. The simulations, using a 10 MHz LTE uplink signal at 2 GHz carrier frequency, confirm this and also show the effect of RF pulse swallowing on the error vector magnitude (EVM).

Silicon photon-counting spectral detectors are candidates for the next generation of medical CT. For silicon detectors, a low noise floor is necessary to obtain good detection efficiency. A low noise floor can be obtained by having a slow shaping filter in the ASIC, but this leads to a long dead-time, thus decreasing the count-rate performance. In this work, we evaluate the benefit of utilizing two sub-channels with different shaping times. It is shown by simulation that utilizing a dual shaper can increase the dose efficiency for equal count-rate capability by up to 17%.

Digital predistortion (DPD) performance for an IEEE 802.11ac WLAN transmitter in 28 nm CMOS, using 20 and 80 MHz bandwidth with 256QAM modulation, is analyzed under different bandwidth limitations. Due to band-limited conditions in the transmitter chain, the DPD linearization performance may be reduced. For a minimum transmitter error vector magnitude (EVM) requirement of -32 dB (2.5%) for 256QAM modulation, a reduction in the maximum linear output power of 1.6 dB due to bandwidth limitations in the transmitter chain is estimated using simulations and measurement results.

Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

In Magnetic Resonance Imaging (MRI) scanners Radio Frequency (RF) signals are important to accurately excite target tissues. RF signals depend on Digital-to-Analog Converters (DAC) output which depends on sequence numbers issued from control room. This paper presents a sigma-delta modulator (SDM), followed by a DAC architecture that can be reconfigured while an MRI scanner is operating and pipelining is not required. The reconfigurable SDM is implemented in a 65nm CMOS technology and operates at an oversampling ratio (OSR) of 64 times. The modulator clocks at 2 GHz frequency with a 1.2-V supply voltage. The modulator occupies an area of 2 9 x 3 2 sq.mu m and consumes 319.1 mW. The proposed SDM-DAC is well-suited for the RF transmitter in the MRI scanner. The reconfigurability feature allows to select different resolutions for various types of RF pulses and can thereby target specific tissues more accurately. (1)

In this paper we present results based on measurements of implantable devices which can be powered externally and communicated with using the near-field communication (NFC) infrastructure. NFC allows us to not have a dedicated gateway and intra-body communication to bridge the data from sensors to phone. In our trials, we have used commercially available sub-components and mounted them on a thin plastic with printed interconnections and coated them for bio-compatibility. Devices were implanted in porcine models during one week. We could during this time measure the in-vivo body temperature through skin and subcutaneous tissue ranging in thickness from some mm to a couple of cm. The implanted sensor devices are mounted on thin, printed-electronics plastic sheets where the coils and conductors are designed with different types of materials. The choice of materials is done in order to offer a low-cost solution to read out data from in-vivo sensors. We compile measured data, practical results and guidelines, together with theoretical results referring to the design of the implanted inductive NFC coil as well as the energy transfer from one mobile device to another.

Asynchronous sigma-delta modulation is investigated as an alternative linearization scheme for all-digital voltage controlled oscillator based analog-to-digital converters, which commonly require digital post processing to achieve good linearity. The modulator output, when used to drive a VCO-based converter, causes the oscillator to operate at two fixed frequencies thereby removing the VCO nonlinearity from the transfer function. A circuit is proposed consisting of a digital block and a passive RC circuit operating as an integrator. Spectre simulation of the design synthesized using a 65 nm standard cell library indicate that a harmonic suppression up to -60 dB is feasible.

A VCO-based ADC is designed and synthesized in a 28 nm FDSOI CMOS process to investigate the scaling benefits of all-digital analog-to-digital conversion. A coarse-fine quantizer is used to obtain high energy efficiency. Common patterns of sample errors at the multi-phase VCO output are identified and mitigated. Final design indicates an ENOB of 13.4 and a Walden FoM of 4.3 fJ/step over a 5 MHz bandwidth while sampling at 150 MHz, according to schematic simulation of the synthesized netlist.

The paper investigates the use of the existing CAD framework for digital circuit synthesis to design and synthesize a select set of mixed-signal functions like analog-to-digital and digital-to-analog conversions. This approach leads to fast and low cost design of technology portable system-on-chip solutions with analog interfaces. Some circuit examples for implementation of data conversion using digital circuits are discussed, leveraging on time-domain signal processing. Some of the signal corruption mechanisms in time-domain signal processing systems are considered in order to suggest adaptations to the existing digital design flow for the synthesis of mixed-signal circuits. As an example to show that high performance data conversion circuits can be realized using low accuracy general purpose components, an ADC is designed and synthesized with the vendor supplied standard cell library in a 65 nm CMOS process. Spectre simulation results show the feasibility of employing a digital CAD framework to synthesize high performance mixed-signal circuits, by applying time-domain signal processing.

VCO-based ADC is an attractive candidate for the synthesis of all-digital ADCs using standard cells. However, the non-linearity of a synthesizable VCO requires digital post-processing to obtain good performance. We propose another solution where the input analog signal is pre-coded into a delta-modulated pulse stream which is used to drive a VCO-based converter. This causes the oscillator to operate at two distinct frequencies thereby eliminating the VCO non-linearity from the converter transfer function. A circuit is proposed that consists of a synthesized digital block realizing all the active parts of the circuit and a passive RC net used as an integrator. Spectre simulation of the netlist synthesized using a 65 nm standard cell library shows a performance of 8.2 bit ENOB over a 3 MHz bandwidth without using any digital post-processing.

An all-digital delay locked loop (DLL) for use in an analog video front end (AFE) is presented. The DLL is designed for a wide input frequency range of 40-300 MHz to cater to a range of different video standards currently in use. The proposed DLL has a closed loop architecture that tracks PVT variations and locks to the input signal in a maximum of nine clock cycles. At its output, the DLL generates 32 uniformly distributed phases of the input clock to provide an optimal sampling point for the analog to digital conversion of the input signal in the AFE.

Synthesis of all-digital ADCs leads to significant reduction in design cost and design time, besides improving cross-technology portability. In this work, an ADC which is fully described in digital HDL is synthesized, placed and routed using standard digital design tools. A VCO-based architecture is chosen for its synthesizability. The design flow employed is discussed. The circuit is synthesized using the standard cell library in a 65 nm CMOS process, delivering a resolution of 9 ENOB over 10 MHz bandwidth according to post layout parasitic extracted simulations using the Spectre simulator. Post synthesis and post place-and-route performances are provided.

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (g_m) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68^o. Sufficient performance is maintained over process, supply voltage and temperature variations.

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

Piecewise affine (PWA) models serve as an important class of models for nonlinear systems. The identification of PWA models is known to be a difficult task and often implies solving a non-convex combinatorial optimization problems. In this paper, we revisit a recently proposed PWA identification method. We do this to give a novel derivation of the identification method and to show that under certain conditions, the method is optimal in the sense that it finds the PWA function that passes through the measurements and has the least number of hinges. We also show how the alternating direction method of multipliers (ADMM) can be used to solve the underlying convex optimization problem.

Time-interleaved ΔΣ DACs have the potential for wideband and high-speed operation. Their SNR is limited by the timing skew between the output delays of the channels to the output. In a two-channel interleaved ΔΣ DAC, the channel skew arises from the duty cycle error in the half sample rate clock. The effects of timing skew error can be mitigated by hold interleaving, digital pre-filtering or compensation in the form of analog post-correction or digital pre-correction. This paper presents a comparative study of these techniques for two-channel interleaving and the trade-offs are investigated. First order FIR pre-filtering is found to be a suitable solution with a moderate DAC matching penalty of one bit. Higher order pre-filtering achieves a near immunity to timing skew at the cost of higher matching penalty. Correction techniques are found to be less effective than pre-filtering and not well suited for high-speed implementation.

In this work we investigate the limitations and describe the operation of passive fully integrated rectifiers in standard CMOS technology for low-voltage piezoelectric harvesters. These harvesters are typical for low-frequency and low-acceleration applications, such as body-motion scenarios, i.e., wearables. We motivate the choice of active rectifiers for low-voltage energy harvesters and techniques to boost the available input voltage to the rectifier. A test circuit recently taped-out in 0.35-μm CMOS is described to illustrate some of the challenges associated with rectifier design for low-voltage energy harvesters. The circuit occupies an area of 210 × 155 μm² and operates at input voltages between 0.6 and 3.3 V. Post-layout simulations shows an efficiency of 79 % at a 0.7-V input.

A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO frequency, i.e., a sub-harmonic frequency of the carrier. As a result, several benefits can be gained. Requiring a sub-harmonic LO (SHLO) relaxes the requirements on the frequency synthesizer circuitry. Moreover, the need for digital power-hungry or analog inductor-based high frequency LO buffers is alleviated. In addition, since rail-to-rail LO signals can be provided easier and with less power consumption at lower frequencies, we can employ passive mixers in the mixer array to improve the power consumption and linearity of the overall transmitter. Multi-phase LO clocks required by the proposed scheme are provided using a delay-locked loops (DLL). The proposed architecture is utilized in design of a WiMedia-UWB direct-conversion TX in a standard 65-nm CMOS technology. The MC simulation results indicate LO leakage of –68 dBc and sideband rejection of –39 dBc. The overall system draw 6.8 mA from a 1.2 V supply.