Department of Electrical Engineering

Lessons TSTE12

Lessons TSTE12 The exercises consists mainly of exercises on the VHDL language. These exercises should be carried out in "pure" VHDL, without the use of HDL Designer (the tool used in the Laborations). Suitable exercises (taken from the course book): Chapter 1: 5, 6 Chapter 2: 4 Chapter 3: 3, 4, 5, 7, 13, 14 Chapter 4: 8, 9, 10 Chapter 5: 8, 10 Chapter 6: 2, 6, 7 Chapter 7: 3 Chapter 8: 5 Chapter 9: 9 Alternative exercises can be found at e.g., www.altera.com (look for Training->University program->Educational materials, tutorials and labs The tutorial material to the classes will found here. Chapter # Chapter name 1 Introduction 2 VHDL introduction 3 HDLdesigner