TSTE12
Handin exercises 2024 part 4 solutions
Solve the handin tasks individually! No cooperation with anyone else!
Theory questions are submitted in LISAM using the comment field.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 (16 with this set) on each of theory and code exercises. The handins are
divided into 3 (4 with this one) sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 4 is due by Monday 4 November 2024 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Solve the tasks individually!!
Good luck!
Theory A
|
What is WRONG related to VHDL?
|
1) Arrays must use integer values as indexes
|
Teori B
|
Which is not an HDL (Hardware Description Language)?
|
2) Ada
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Theory C
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What is WRONG related to processes in VHDL?
|
1) Proceses can have both wait statements and a non-empty sensitivity list
|
Theory D
|
What is NOT a valid identifier in VHDL'87?
|
3) register
|
Exercise Code A
source file: INL4_KA.vhdl Name of the source file
Entity: INL4_KA Name of the entity
architecture: KA Name of the architecture
Inputs: E data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, std_logic_vector(2 downto 0)
Behaviour: Create a positive edge (rising edge) clocked counter with asynchronous
reset R and count enable E that counts with step size 3. If R = '1' then
output Q = "000". If a rising edge on C and R='0' and E='1'
then increment the Q value by 3. Incrementing "111" by 3 => "010",
incrementing "110" by 3 => "001", incrementing "101" by 3 => "000".
Example: Q="101", R='0', E='1', rising edge on C => Q = "000"
Q="100", R='1', => Q = "000"
Q="010", R='0', E='1', rising edge on C => Q = "101"
Q="001", R='0', E='0', rising edge on C => Q = "001"
Solution
========
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity INL4_KA is
port(
E, R, C : in bit;
Q : out std_logic_vector(2 downto 0));
end entity;
architecture KA of INL4_KA is
begin
process(C,R)
variable count : unsigned(2 downto 0);
begin
if R = '1' then
count := (others => '0');
elsif rising_edge(C) then
if E = '1' then
count := count + 3;
end if;
end if;
Q <= std_logic_vector(count);
end process;
end architecture;
Exercise Code B
source file: INL4_KB.vhdl Name of the source file
Package: INL4_KB Name of the package
function: KB Name of the function
Inputs: A data in, signal, bit_vector (unconstrained size)
Outputs: data out, bit
Behaviour: Create a package with a function KB that determines if the
number of 1:s in A is odd or even. Return 0 if the number of
ones in A is even, return 1 if the number of ones in A is odd.
Example: A="0011" => KB(A)='0'
A="111" => KB(A)='1'
A="1101" => KB(A)='1'
A="0" => KB(A)='0'
Solution
========
package INL4_KB is
function KB (signal A : bit_vector) return bit;
end package;
package body INL4_KB is
function KB(signal A : bit_vector) return bit is
variable index : integer;
variable odd_ones : bit;
begin
odd_ones := '0';
for index in A'range loop
if A(index) = '1' then
odd_ones := not odd_ones;
end if;
end loop;
return odd_ones;
end function;
end package body;
Exercise Code C
source file: INL4_KC.vhdl Name of the source file
Entity: INL4_KC Name of the entity
architecture: KC Name of the architecture
Inputs: A data in, bit_vector(1 to 8)
Outputs: Y data out, bit
Behavour: Create a gate that outputs a '1' if there are 5 or more bits
in A that are '1'.
Example: A="11000111" => Y = '1'
A="11010111" => Y = '1'
A="10101010" => Y = '0'
A="01000100" => Y = '0'
Solution
========
entity INL4_KC is
port(
A : in bit_vector(1 to 8);
Y : out bit);
end entity;
architecture KC of INL4_KC is
begin
process(A)
variable count : integer;
variable index : integer;
begin
count := 0;
for index in 1 to 8 loop
if A(index) = '1' then
count := count + 1;
end if;
end loop;
if count >= 5 then
Y <= '1';
else
Y <= '0';
end if;
end process;
end architecture;
Exercise Code D
source file: INL4_KD.vhdl Name of the source file
Entity: INL4_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(1 downto 0)
B data in, bit
Outputs: Y data out, bit
Behaviour: Create a detector that when B have a positive edge checks if A has changed
during the previous 20 ns. If A did change then output '1' while
B is '1', else output '0'. Output '0' when B is '0'.
Example: A="11", B='0' for 300 ns. Y=0. B change to '1' => Y still '0'
A="01", B='0' for 200 ns, A="11" for 10 ns, B change to '1' => Y = '1' while B='1'
B='0' => Y='0'
Solution
========
entity INL4_KD is
port(
A : in bit_vector(1 downto 0);
B : in bit;
Y : out bit);
end entity;
architecture KD of INL4_KD is
begin
process(B)
begin
if B'event and (B = '1') then
if A'stable(20 ns) then
Y <= '0';
else
Y <= '1';
end if;
else
Y <= '0';
end if;
end process;
end architecture;