| What is WRONG regarding signals in VHDL? |
1) Signals can be defined inside architecture declaration area 2) Entity ports are signals 3) Signals can be assigned values from constants 4) Signals are always assigned a value at simulation start |
| How many different architectures can be declared for an entity? |
1) 1 2) 2 3) 16 4) no defined upper limit |
| Which one is not a predefined array attribute in the VHDL language? |
1) 'first 2) 'left 3) 'length 4) 'low |
| What is WRONG regarding FPGA hardware? |
1) Most FPGA:s are built on look-up tables and flipflops 2) FPGA:s often support a different internal clock frequency 3) FPGA:s contain a microprocessor that is running the VHDL code 4) FPGA:s often include dedicated multipliers structures |
source file: INL2_KA.vhdl Name of the source file.
Entity: INL2_KA Name of the entity
architecture: KA Name of the architecture
Inputs: D data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, bit_vector(6 downto 2)
Behaviour: Create a negative edge trigged resettable shift register.
When there is a falling edge on C and R='1' then set Q to
"00000". If there is a falling edge on C and R='0' then
left shift Q one step and put input from D into
rightmost position in Q.
Example: Q="10101", R='1', falling edge on C => Q="00000"
Q="00100", R='0', D='1', falling edge on C => Q="01001"
source file: INL2_KB.vhdl Name of the source file
Entity: INL2_KB Name of the entity
architecture: KB Name of the architecture
Inputs: D data in, bit_vector(2 to 4)
C data in, bit
R data in, bit
Outputs: Q data out, bit_vector(2 to 4)
Behavour: Create a 3-bit positive edge triggered register
with asynchronous reset. If R='1' then set Q to "000".
If there is a rising edge on C and R='0' then copy
the value on D to Q.
Example: R='1' => Q="000"
R='0', D="011", rising edge on C => Q="011"
source file: INL2_KC.vhdl Name of the source file
Entity: INL2_KC Name of the entity
architecture: KC Name of the architecture
Inputs: C data in, bit
R data in, bit
Outputs: Q data out, std_logic_vector(3 downto 1)
Behaviour: Create a positive edge triggered 3 bit counter with
synchronous reset. If rising edge on C and R='1' then
Q="000". If a rising edge on C, and R='0' then
increment Q by 1. Incrementing "111" generates "000".
Example: R='0',Q="010",rising edge on C => Q="010"Q="011"
R='1', rising edge on C => Q="000"
R='0',Q="110",rising edge on C => Q="111"
source file: INL2_KD.vhdl Name of the source file
Entity: INL2_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, std_logic
B data in, std_logic
Outputs: Y data out, std_logic
Behavour: Create a 2-input OR gate where the output strength
(use of 0/1, L/H or X) is based on the input strength.
If both A and B have strong values ('0' or '1') then
output a '1' or '0' that match an or function.
If one or more inputs have a 'L' or 'H' and the other
input has a value of '0', '1', 'L', or 'H' then output
a 'L' or 'H', where 'L' is seen as a logic 0, and 'H'
is seen as a logic 1.
If any of the inputs are not '0', '1', 'L' or 'H' then
output 'X'.
Example: A='1', B='0' => Y='1'
A='U', B='1' => Y='X'
A='L', B='0' => Y='L'