IMPORTANT: Handin tasks are INDIVIDUAL. Do NOT work together to solve these questions!

Submit all theory question answers in one submission into Lisam. Indicate answers using one line per question, indicating which question (A-D) and which of the multiple choices (1-4) that is your answer to each question.

To pass on the handin exercises it is required to reach 9 correct exercises of 12 on each of theory and code exercises. The handins are divided into 3 sets of questions with 4 points of theori and 4 points of coding on each. Read closely the instructions on the handin main page!

Note the time schedule!
Handin exercise answers must be submitted at latest by the deadline on the given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to open a shell window to work from.

Handin part 1 is due by Monday 23 September 2024 at 23.30!

The results will be available in the lisam submission.

Note:
   Read the instructions at the main page!!
   Ask if any difficulties or uncertainty!!

Good luck!

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Theory A

What is WRONG related to VHDL?

3) The language can only process data presented as bits

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Theory B

Which datatype was NOT part of the original VHDL standard from 1987?

1) mvl4

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Theory C

Which library/libraries are always available?

4) STD and WORK

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Teori D

What is WRONG regarding variable in VHDL? (NOTE: Error in the question, two correct answers, full credit if answer either of these)

1) Variable assignments always includes a delay 2) Variables can not be assigned a value from a signal

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Exercise Code A

   source file: INL1_KA.vhdl   Name of the source file
        Entity: INL1_KA        Name of the entity
  architecture: KA             Name of the architecture
        Inputs: A              data in,  bit_vector(3 downto 0)
       Outputs: Y              data out, bit

      Behavour: Create a 4-input NAND gate. 

       Example: A="0000" => Y='1'
                A="1101" => Y='1'
                A="1111" => Y='0'


Solution
========

entity INL1_KA is
  port(
    A : in bit_vector(3 downto 0);
    Y : out bit);
end entity;

architecture KA of INL1_KA is
begin
  Y <= not (A(3) and A(2) and A(1) and A(0));
end architecture;

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Exercise Code B

   source file: INL1_KB.vhdl   Name of the source file
        Entity: INL1_KB        Name of the entity
  architecture: KB             Name of the architecture
        Inputs: A              data in, bit
                B              data in, bit
       Outputs: Y              data out, bit

      Behavour: Create a 2-input AND gate with a 3 ns output delay.
                Any output pulse shorter than 3 ns should be filtered
                out.

       Example: A='1', B='1' for a long time => Y='1'
                A='1', B='1', B change to '0' at time 2 ns, B change to '1' at 4 ns => Y='1' (no change)
                A='1', B='1', A change to '0' at time 6 ns => Y='0' from time 9 ns


Solution
========
    
entity INL1_KB is
  port(
    A : in bit;
    B : in bit;
    Y : out bit);
end entity;

architecture KB of INL1_KB is
begin
  Y <= A and B after 3 ns;
end architecture;
    

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Exercise Code C

   source file: INL1_KC.vhdl   Name of the source file
        Entity: INL1_KC        Name of the entity
  architecture: KC             Name of the architecture
        Inputs: A              data in, bit
                B              data in, bit
                C              data in, bit
       Outputs: Y              data out, bit

     Behaviour: Output a '1' only if exactly one of the inputs is '1', output '0' otherwise

       Example: A='0', B='1', C='1' => Y='0'
                A='1', B='0', C='0' => Y='1'
                A='1', B='1', C='1' => Y='0'

Solution
========
      
entity INL1_KC is
  port(
    A : in bit;
    B : in bit;
    C : in bit;
    Y : out bit);
end entity;

architecture KC of INL1_KC is
  signal selectvector : bit_vector(1 to 3);
begin
  selectvector <= A & B & C;
  
  with selectvector select
    Y <= '1' when "100"|"010"|"001",
    '0' when others;
    
end architecture;
  

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Exercise Code D

   source file: INL1_KD.vhdl   Name of the source file.
        Entity: INL1_KD        Name of the entity
  architecture: KD             Name of the architecture
        Inputs: A              data in,  bit_vector(0 to 1)
                B              data in,  bit
       Outputs: Y              data out, bit


     Behaviour: Create a multiplexer where B selects which element in A
                to output on Y. B='0' select A(0) and B='1' selects A(1).

       Example: A="01",B='1' => Y='1'
                A="10",B='1' => Y='0'
   

Solution
=======

entity INL1_KD is
  port(
    A : in bit_vector(0 to 1);
    B : in bit;
    Y : out bit);
end entity;

architecture KD of INL1_KD is
begin
  Y <= A(0) when B='0' else A(1);
end architecture;
	

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