TSTE12
Individual handin exercises retake 2024-01-02 solutions
Solve the handin tasks individually! No cooperation with anyone else is allowed!
Theory questions are submitted in Lisam using the comment field.
A pass on this handin exercise requires atleast 6 correct
exercises out of 9 on each of theory and code exercises respectively.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place and compiled at latest by the deadline on the given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Exercise retake part is due by Wednesday 10 January 2024 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Solve the tasks individually!!
Good luck!
Theory A
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What is wrong related to signals in VHDL?
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3) Signals can be declared in the declaration area of a processes
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Theory B
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What is wrong regarding VHDL timing?
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1) Delta delays will add up to a standard delay
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Theory C
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What is the maximum number of different architectures connect to an entity declaration?
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4) not defined
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Theory D
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What is wrong related to variables?
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4) Variable declarations does not include the type (note wrong numbering)
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Theory E
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What is wrong regarding processes?
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4) A process is required to have a sensitivity list (note wrong numbering)
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Theory F
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What is not a valid VHDL identifier (VHDL standard 1987 version)?
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2) register
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Theory G
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What is wrong related to the VHDL language?
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1) Data types are automatically translated to match the variable data type
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Theory H
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What is wrong regarding VHDL synthesis?
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1) For and loop statements in a process can not be synthesized
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Teori J
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What wrong related to FPGA hardware?
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1) The synthesis output is executed by a processor in the FPGA chip
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Exercise Code A
source file: INL5_KA.vhdl Name of the source file.
Entity: INL5_KA Name of the entity
Architecture: KA Name of the architecture
Inputs: A data in, bit_vector(5 downto 2)
Outputs: Y data out, bit
Behavour: Create a 4-input NOR-gate.
Example: A="0100" => Y='0',
A="1011" => Y='0',
A="0000" => Y='1'
Solution
========
entity INL5_KA is
port (
A : in bit_vector(5 downto 2);
Y : out bit);
end entity;
architecture KA of INL5_KA is
begin
Y <= not (A(5) or A(4) or A(3) or A(2));
end KA;
Exercise Code B
source file: INL5_KB.vhdl Name of the source file.
Entity: INL5_KB Name of the entity
Architecture: KB Name of the architecture
Inputs: A data in, integer
Level generic, integer, default value 5
Outputs: Y data out, bit
Behavour: An level checker circuit with configurable level definition.
Output '1' if A > Level, otherwise output '0'.
Example: Level=5, A=9 => Y='1'
Level=11, A=11 => Y='0'
Level=-6, A=-7 => Y='0'
Solution
========
entity INL5_KB is
generic (
Level : integer := 5);
port (
A : in integer;
Y : out bit);
end entity;
architecture KB of INL5_KB is
begin
Y <= '1' when A > Level else '0';
end KB;
Exercise Code C
source file: INL5_KC.vhdl Name of the source file.
Package: INL5_KC Name of the package
Function: KC Name of the function
Inputs: A data in, bit
B data in, bit
C data in, bit
Outputs: data out, std_logic
Behavour: Create a packet containing a function KC that checks that
A, B and C have the same value. Return the value of A if
A, B, and C have the same value, otherwise return 'X'.
Examples: A='1',B='1',C='1' => '1'
A='0',B='0',C='1' => 'X'
Solution
========
library ieee;
use ieee.std_logic_1164.all;
package INL5_KC is
function KC(A,B,C : in bit) return std_logic;
end package;
package body INL5_KC is
function KC(A,B,C : in bit) return std_logic is
begin
if (A = B) and (A = C) then
if A = '1' then
return '1';
else
return '0';
end if;
else
return 'X';
end if;
end;
end;
Exercise Code D
source file: INL5_KD.vhdl Name of the source file.
Entity: INL5_KD Name of the entity
Architecture: KD Name of the architecture
Inputs: A data in, std_logic_vector(1 to 2)
Out: Y data out, std_logic
Behaviour: 2-input NAND-gate. An input of '0' or 'L' are seen as the
logic level 0, and the input values '1' and 'H' are seen
as the logic level 1. Output '1' or '0' according to the
logic function if both inputs contain values from the set
'0','1','L', or 'H'. If any of A or B contins any other
value then output 'X'.
Example: A="W0" => Y='X'
A="H1" => Y='0'
A="00" => Y='1'
A="HL" => Y='1'
Solution
========
library ieee;
use ieee.std_logic_1164.all;
entity INL5_KD is
port(
A : in std_logic_vector(1 to 2);
Y : out std_logic);
end entity;
architecture KD of INL5_KD is
begin
with A select
Y <=
'0' when "11" | "H1" | "1H" | "HH",
'1' when "00" | "L0" | "0L" | "LL" |
"01" | "L1" | "0H" | "LH" |
"10" | "H0" | "1L" | "HL",
'X' when others;
end KD;
Exercise Code E
source file: INL5_KE.vhdl Name of the source file.
Entity: INL5_KE Name of the entity
Architecture: KE Name of the architecture
Inputs: D data in, bit_vector(4 downto 1)
S data in, bit
C data in, bit
Outputs: Q data out, bit_vector(4 downto 1)
Behavour: A positive edge trigged 4-bit register with synchronous set.
If a rising edge on C and S = '1' then Q = "1111". If a rising
edge on C and S = '0' then copy the value from D to Q.
Example: Rising edge on C, S='0' and D="0011" => Q="0011"
Rising edge on C, S='1' => Q="1111"
Solution
========
entity INL5_KE is
port (
D : in bit_vector(4 downto 1);
S : in bit;
C : in bit;
Q : out bit_vector(4 downto 1));
end entity;
architecture KE of INL5_KE is
begin
process(C)
begin
if C'event and (C='1') then
if S='1' then
Q <= "1111";
else
Q <= D;
end if;
end if;
end process;
end KE;
Exercise Code F
source file: INL5_KF.vhdl Name of the source file.
Entity: INL5_KF Name of the entity
Architecture: KF Name of the architecture
Inputs: C data in, bit
L data in, bit
D data in, bit_vector(2 downto 0)
Outputs: Q data out, bit_vector(2 downto 0)
Behavour: Synchronous negative edge trigged binary upcounter with synchronous
load. If L='1' and negative edge on C then copy D to Q. If L='0' and
negative edge on C then increment the binary value of Q. Q="111" is
incremented to "000".
Example: L='1', D="101", negative edge on C => Q="101"
L='0', negative edge on C, Q="010" => Q="011"
L='0', negative edge on C, Q="111" => Q="000"
Solution
========
library ieee;
use ieee.numeric_bit.all;
entity INL5_KF is
port (
C : in bit;
L : in bit;
D : in bit_vector(2 downto 0);
Q : out bit_vector(2 downto 0));
end entity;
architecture KF of INL5_KF is
begin
process(C)
variable Q_tmp : unsigned(2 downto 0);
begin
if C'event and (C='0') then
if L='1' then
Q_tmp := unsigned(D);
else
Q_tmp := Q_tmp + 1;
end if;
end if;
Q <= bit_vector(Q_tmp);
end process;
end KF;
Exercise Code G
source file: INL5_KG.vhdl Name of the source file.
Entity: INL5_KG Name of the entity
Architecture: KG Name of the architecture
Inputs: D data in, bit
C data in, bit
Outputs: Q data out, bit_vector(1 to 3)
Behavour: A positive edge trigged shift register. If positive edge on
C then shift register to the left, and put value of D on the
rightmost position of the register.
Example: D='1', postive edge on C, Q="000" => Q="001"
D='0', postive edge on C, Q="101" => Q="010"
Solution
========
entity INL5_KG is
port (
D : in bit;
C : in bit;
Q : out bit_vector(1 to 3));
end entity;
architecture KG of INL5_KG is
begin
process(C)
variable Q_tmp : bit_vector(1 to 3);
begin
if C'event and (C = '1') then
Q_tmp := Q_tmp(2 to 3) & D;
end if;
Q <= Q_tmp;
end process;
end KG;
Exercise Code H
source file: INL5_KH.vhdl Name of the source file.
Entity: INL5_KH Name of the entity
Architecture: KH Name of the architecture
Inputs: A data in, bit
B data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, bit
Behavour: Positive edge trigged state machine of Moore type with asynchronous
reset input. The state machine should flip (0->1 or 1->0) then output
when A=B in the previous clock cycle and A!=B in the current clock
cycle.
If R='1' then set Q='0', and assume A!=B in previous clock cycle.
Example: (assume here these are in a sequence)
R='1',A='0',B='1' => Q='0'
R='0',A='0',B='0' => Q='0'
R='0',A='1',B='0' rising edge on C => Q='0'
R='0',A='0',B='0' rising edge on C => Q='0'
R='0',A='1',B='0' rising edge on C => Q='1'
R='0',A='1',B='1' rising edge on C => Q='1'
R='0',A='0',B='0' rising edge on C => Q='1'
R='0',A='0',B='1' rising edge on C => Q='0'
Solution
========
entity INL5_KH is
port (
A : in bit;
B : in bit;
R : in bit;
C : in bit;
Q : out bit);
end entity;
architecture KH of INL5_KH is
begin
process(C,R)
variable Q_tmp : bit;
variable AB_prev_equal : bit;
begin
if R='1' then
Q_tmp := '0';
AB_prev_equal := '0';
elsif C'event and C='1' then
if AB_prev_equal = '1' then
Q_tmp := A xor B; -- xor produce 1 if nonequal
else
Q_tmp := '0';
end if;
AB_prev_equal := not (A xor B);
end if;
Q <= Q_tmp;
end process;
end KH;
Exercise Code J
source file: INL5_KJ.vhdl Name of the source file.
Entity: INL5_KJ Name of the entity
Architecture: KJ Name of the architecture
Inputs: A data in, bit_vector(2 downto 1)
B data in, bit_vector(2 downto 1)
Outputs: Y data out, bit_vector(2 downto 1)
Behavour: Instanciate the component work.INL5_KJ_test(behav) into the
design. The component will have the same inputs and outputs as
INL5_KJ. Connect input A to input A on INL5_KJ_test. The Y
output from INL5_KJ_test should inverted before
reaching the Y output of INL5_KJ.
Example: Assume INL5_KJ_test calculates the bitwise AND function between A and B
(A(2) and B(2); A(1) and B(1)) then A = "01", B = "11" => Y = "10"
Note: Missing statement that B should attach to B on INL5_KJ_test
Solution
========
entity INL5_KJ is
port (
A : in bit_vector(2 downto 1);
B : in bit_vector(2 downto 1);
Y : out bit_vector(2 downto 1));
end entity;
architecture KJ of INL5_KJ is
component INL5_KJ_test is
port (
A : in bit_vector(2 downto 1);
B : in bit_vector(2 downto 1);
Y : out bit_vector(2 downto 1));
end component;
for U1: INL5_KJ_test use entity work.INL5_KJ_test(behav);
signal Y_tmp : bit_vector(2 downto 1);
begin
U1: INL5_KJ_test
port map (
A => A,
B => B,
Y => Y_tmp);
Y <= not Y_tmp;
end KJ;