| What is wrong related to signals in VHDL? |
1) Signals are always initilized at simulation start 2) Signals can be assigned values from variables 3) Signals can be declared in the declaration area of a processes 4) Signals can be assigned values from constants |
| What is wrong regarding VHDL timing? |
1) Delta delays will add up to a standard delay 2) Signal updates are always delayed 3) Processes can contain wait statements 4) Attributes can be used to check old values of a signal |
| What is the maximum number of different architectures connect to an entity declaration? |
1) 1 2) 2 3) 16 4) not defined |
| What is wrong related to variables? |
4) Variable declarations does not include the type 1) Variables can be declared in functions 2) Variables can be assigned to the value of a constant 3) Variable declaration can define an initialisation value |
| What is wrong regarding processes? |
4) A process is required to have a sensitivity list 1) Procedures can be declared in a process 2) The process contains sequential code 3) Variables can be declared in processes |
| What is not a valid VHDL identifier (VHDL standard 1987 version)? |
1) One_fine_design 2) register 3) MC68000 4) address_bus |
| What is wrong related to the VHDL language? |
1) Data types are automatically translated to match the variable data type 2) Packages are used to support information hiding 3) Operators can be redefined (overloading) 4) Inheritence is not supported |
| What is wrong regarding VHDL synthesis? |
1) For and loop statements in a process can not be synthesized 2) Only a subset of the language can be synthesized 3) Fixed delays in signal assignments are ignored by synthesis tools 4) Integers can be used for synthesis |
| What wrong related to FPGA hardware? |
1) The synthesis output is executed by a processor in the FPGA chip 2) An FPGA can use a different clock frequency internally 3) RAM based FPGAs must be configured every time power is applied 4) FPGA hardware often contains features to speed up addition |
source file: INL5_KA.vhdl Name of the source file.
Entity: INL5_KA Name of the entity
Architecture: KA Name of the architecture
Inputs: A data in, bit_vector(5 downto 2)
Outputs: Y data out, bit
Behavour: Create a 4-input NOR-gate.
Example: A="0100" => Y='0',
A="1011" => Y='0',
A="0000" => Y='1'
source file: INL5_KB.vhdl Name of the source file.
Entity: INL5_KB Name of the entity
Architecture: KB Name of the architecture
Inputs: A data in, integer
Level generic, integer, default value 5
Outputs: Y data out, bit
Behavour: An level checker circuit with configurable level definition.
Output '1' if A > Level, otherwise output '0'.
Example: Level=5, A=9 => Y='1'
Level=11, A=11 => Y='0'
Level=-6, A=-7 => Y='0'
source file: INL5_KC.vhdl Name of the source file.
Package: INL5_KC Name of the package
Function: KC Name of the function
Inputs: A data in, bit
B data in, bit
C data in, bit
Outputs: data out, std_logic
Behavour: Create a packet containing a function KC that checks that
A, B and C have the same value. Return the value of A if
A, B, and C have the same value, otherwise return 'X'.
Examples: A='1',B='1',C='1' => '1'
A='0',B='0',C='1' => 'X'
source file: INL5_KD.vhdl Name of the source file.
Entity: INL5_KD Name of the entity
Architecture: KD Name of the architecture
Inputs: A data in, std_logic_vector(1 to 2)
Out: Y data out, std_logic
Behaviour: 2-input NAND-gate. An input of '0' or 'L' are seen as the
logic level 0, and the input values '1' and 'H' are seen
as the logic level 1. Output '1' or '0' according to the
logic function if both inputs contain values from the set
'0','1','L', or 'H'. If any of A or B contins any other
value then output 'X'.
Example: A="W0" => Y='X'
A="H1" => Y='0'
A="00" => Y='1'
A="HL" => Y='1'
source file: INL5_KE.vhdl Name of the source file.
Entity: INL5_KE Name of the entity
Architecture: KE Name of the architecture
Inputs: D data in, bit_vector(4 downto 1)
S data in, bit
C data in, bit
Outputs: Q data out, bit_vector(4 downto 1)
Behavour: A positive edge trigged 4-bit register with synchronous set.
If a rising edge on C and S = '1' then Q = "1111". If a rising
edge on C and S = '0' then copy the value from D to Q.
Example: Rising edge on C, S='0' and D="0011" => Q="0011"
Rising edge on C, S='1' => Q="1111"
source file: INL5_KF.vhdl Name of the source file.
Entity: INL5_KF Name of the entity
Architecture: KF Name of the architecture
Inputs: C data in, bit
L data in, bit
D data in, bit_vector(2 downto 0)
Outputs: Q data out, bit_vector(2 downto 0)
Behavour: Synchronous negative edge trigged binary upcounter with synchronous
load. If L='1' and negative edge on C then copy D to Q. If L='0' and
negative edge on C then increment the binary value of Q. Q="111" is
incremented to "000".
Example: L='1', D="101", negative edge on C => Q="101"
L='0', negative edge on C, Q="010" => Q="011"
L='0', negative edge on C, Q="111" => Q="000"
source file: INL5_KG.vhdl Name of the source file.
Entity: INL5_KG Name of the entity
Architecture: KG Name of the architecture
Inputs: D data in, bit
C data in, bit
Outputs: Q data out, bit_vector(1 to 3)
Behavour: A positive edge trigged shift register. If positive edge on
C then shift register to the left, and put value of D on the
rightmost position of the register.
Example: D='1', postive edge on C, Q="000" => Q="001"
D='0', postive edge on C, Q="101" => Q="010"
source file: INL5_KH.vhdl Name of the source file.
Entity: INL5_KH Name of the entity
Architecture: KH Name of the architecture
Inputs: A data in, bit
B data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, bit
Behavour: Positive edge trigged state machine of Moore type with asynchronous
reset input. The state machine should flip (0->1 or 1->0) then output
when A=B in the previous clock cycle and A!=B in the current clock
cycle.
If R='1' then set Q='0', and assume A!=B in previous clock cycle.
Example: (assume here these are in a sequence)
R='1',A='0',B='1' => Q='0'
R='0',A='0',B='0' => Q='0'
R='0',A='1',B='0' rising edge on C => Q='0'
R='0',A='0',B='0' rising edge on C => Q='0'
R='0',A='1',B='0' rising edge on C => Q='1'
R='0',A='1',B='1' rising edge on C => Q='1'
R='0',A='0',B='0' rising edge on C => Q='1'
R='0',A='0',B='1' rising edge on C => Q='0'
source file: INL5_KJ.vhdl Name of the source file.
Entity: INL5_KJ Name of the entity
Architecture: KJ Name of the architecture
Inputs: A data in, bit_vector(2 downto 1)
B data in, bit_vector(2 downto 1)
Outputs: Y data out, bit_vector(2 downto 1)
Behavour: Instanciate the component work.INL5_KJ_test(behav) into the
design. The component will have the same inputs and outputs as
INL5_KJ. Connect input A to input A on INL5_KJ_test. The Y
output from INL5_KJ_test should inverted before
reaching the Y output of INL5_KJ.
Example: Assume INL5_KJ_test calculates the bitwise AND function between A and B
(A(2) and B(2); A(1) and B(1)) then A = "01", B = "11" => Y = "10"