TSTE12
Handin exercises 2023 part 4 solutions
Solve the handin tasks individually! No cooperation with anyone else!
Theory questions are submitted in LISAM using the comment field.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 (16 with this set) on each of theory and code exercises. The handins are
divided into 3 (4 with this one) sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 4 is due by Monday 30 October 2023 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Solve the tasks individually!!
Good luck!
Theory A
|
What is NOT a valid identifier in VHDL'87?
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1) bus
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Theory B
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What is WRONG related to VHDL?
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1) All VHDL code can be synthesized to FPGA hardware
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Teori C
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Which is not an HDL (Hardware Description Language)?
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4) html
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Theory D
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What is WRONG related to processes in VHDL?
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1) Executing the statements inside the process body (excluding wait statements) will increase time
|
Exercise Code A
source file: INL4_KA.vhdl Name of the source file
Package: INL4_KA Name of the package
function: KA Name of the function
Inputs: A data in, signal, std_logic_vector (unconstrained size)
B data in, signal, std_logic
Outputs: data out, integer
Behaviour: Create a package with a function KB that counts the
number of time the value of B is found in the vector A.
Example: A="00X01Z11", B='1' => KA(A,B)=3
A="111", B='X' => KA(A,B)=0
A="L1L01", B='0' => KA(A,B)=2
A="Z", B='Z' => KA(A,B)=1
Solution
========
library ieee;
use ieee.std_logic_1164.all;
package INL4_KA is
function KA ( signal a : std_logic_vector; signal B : std_logic) return integer;
end package;
package body INL4_KA is
function KA ( signal A : std_logic_vector ; signal B : std_logic) return integer is
variable count : integer := 0;
begin
for i in A'range loop
if A(i) = B then
count := count + 1;
end if;
end loop;
return count;
end;
end package body;
Exercise Code B
source file: INL4_KB.vhdl Name of the source file
Entity: INL4_KB Name of the entity
architecture: KB Name of the architecture
Inputs: A data in, bit_vector(1 to 5)
Outputs: Y data out, bit
Behavour: Create a gate that outputs a '1' if there is more bits
in A that are '1' than that are '0'.
Example: A="11011" => Y = '1'
A="01111" => Y = '1'
A="10000" => Y = '0'
A="01100" => Y = '0'
Solution
========
entity INL4_KB is
port (
A : in bit_vector(1 to 5);
Y : out bit);
end entity;
architecture KB of INL4_KB is
begin
process(A)
variable count : integer;
begin
count := 0;
for i in 1 to 5 loop
if A(i) = '1' then
count := count + 1;
end if;
end loop;
if count > 2 then
Y <= '1';
else
Y <= '0';
end if;
end process;
end architecture;
Exercise Code C
source file: INL4_KC.vhdl Name of the source file
Entity: INL4_KC Name of the entity
architecture: KC Name of the architecture
Inputs: E data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, std_logic_vector(3 downto 1)
Behaviour: Create a negative edge (falling edge) clocked counter with asynchronous
reset R and count enable E that counts with step size 3. If R = '1' then
output Q = "0000". If a falling edge on C and R='0' and E='1'
then increment the Q value by 3. Incrementing "111" by 3 => "010",
incrementing "110" by 3 => "001", incrementing "101" by 3 => "000".
Example: Q="101", R='0', E='1', falling edge on C => Q = "000"
Q="100", R='1', => Q = "000"
Q="010", R='0', E='1', falling edge on C => Q = "101"
Q="001", R='0', E='0', falling edge on C => Q = "001"
Solution
========
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity INL4_KC is
port (
E : in bit;
R : in bit;
C : in bit;
Q : out std_logic_vector(3 downto 1));
end entity;
architecture KC of INL4_KC is
begin
process(C,R)
variable Q_tmp : unsigned(3 downto 1);
begin
if R = '1' then
Q_tmp := (others => '0');
elsif falling_edge(C) then
if E = '1' then
Q_tmp := Q_tmp + 3;
end if;
end if;
Q <= std_logic_vector(Q_tmp);
end process;
end architecture;
Exercise Code D
source file: INL4_KD.vhdl Name of the source file
Entity: INL4_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(2 downto 0)
B data in, bit
Outputs: Y data out, bit
Behaviour: Create a detector that when B have a positive edge checks if A has changed
during the previous 50 ns. If A did change then output '1' while
B is '1', else output '0'. Output '0' when B is '0'.
Example: A="101", B='0' for 300 ns. Y=0. B change to '1' => Y still '0'
A="011", B='0' for 200 ns, A="101" for 20 ns, B change to '1' => Y = '1' while B='1'
B='0' => Y='0'
Solution
========
entity INL4_KD is
port (
A : in bit_vector(2 downto 0);
B : in bit;
Y : out bit);
end entity;
architecture KD of INL4_KD is
begin
process(A,B)
begin
if rising_edge(B) then
if A'stable(50 ns) then
Y <= '0';
else
Y <= '1';
end if;
end if;
if B = '0' then
Y <= '0';
end if;
end process;
end architecture;