What is NOT a valid identifier in VHDL'87? |
1) bus 2) aduio_src 3) spi_0 4) RpI |
What is WRONG related to VHDL? |
1) All VHDL code can be synthesized to FPGA hardware 2) File I/O is supported. 3) Data types can be defined inside a process 4) Constants must have a data type |
Which is not an HDL (Hardware Description Language)? |
1) SystemVerilog 2) Verilog 3) System-C 4) html |
What is WRONG related to processes in VHDL? |
1) Executing the statements inside the process body (excluding wait statements) will increase time 2) Variables in processes keep their values when the process restarts 3) Statements inside the process are sequential statements 4) Processes without a sensitivity list will be restarted immediately |
source file: INL4_KA.vhdl Name of the source file Package: INL4_KA Name of the package function: KA Name of the function Inputs: A data in, signal, std_logic_vector (unconstrained size) B data in, signal, std_logic Outputs: data out, integer Behaviour: Create a package with a functionKBKA that counts the number of time the value of B is found in the vector A. Example: A="00X01Z11", B='1' => KA(A,B)=3 A="111", B='X' => KA(A,B)=0 A="L1L01", B='0' => KA(A,B)=2 A="Z", B='Z' => KA(A,B)=1
source file: INL4_KB.vhdl Name of the source file Entity: INL4_KB Name of the entity architecture: KB Name of the architecture Inputs: A data in, bit_vector(1 to 5) Outputs: Y data out, bit Behavour: Create a gate that outputs a '1' if there is more bits in A that are '1' than that are '0'. Example: A="11011" => Y = '1' A="01111" => Y = '1' A="10000" => Y = '0' A="01100" => Y = '0'
source file: INL4_KC.vhdl Name of the source file Entity: INL4_KC Name of the entity architecture: KC Name of the architecture Inputs: E data in, bit R data in, bit C data in, bit Outputs: Q data out, std_logic_vector(3 downto 1) Behaviour: Create a negative edge (falling edge) clocked counter with asynchronous reset R and count enable E that counts with step size 3. If R = '1' then output Q = "0000". If a falling edge on C and R='0' and E='1' then increment the Q value by 3. Incrementing "111" by 3 => "010", incrementing "110" by 3 => "001", incrementing "101" by 3 => "000". Example: Q="101", R='0', E='1', falling edge on C => Q = "000" Q="100", R='1', => Q = "000" Q="010", R='0', E='1', falling edge on C => Q = "101" Q="001", R='0', E='0', falling edge on C => Q = "001"
source file: INL4_KD.vhdl Name of the source file Entity: INL4_KD Name of the entity architecture: KD Name of the architecture Inputs: A data in, bit_vector(2 downto 0) B data in, bit Outputs: Y data out, bit Behaviour: Create a detector that when B have a positive edge checks if A has changed during the previous 50 ns. If A did change then output '1' while B is '1', else output '0'. Output '0' when B is '0'. Example: A="101", B='0' for 300 ns. Y=0. B change to '1' => Y still '0' A="011", B='0' for 200 ns, A="101" for 20 ns, B change to '1' => Y = '1' while B='1' B='0' => Y='0'