TSTE12
Handin exercises 2023 part 3 solutions
Solve the handin tasks individually! No cooperation with anyone else!
Theory questions are submitted in LISAM using the comment field.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 on each of theory and code exercises. The handins are
divided into 3 sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 3 is due by Monday 16 October 2023 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Solve the tasks individually!!
Good luck!
Theory A
|
What libraries does not need to be declared (are always availabe)?
|
4) work and std
|
Theory B
|
What is WRONG regarding subprograms in VHDL?
|
2) Functions does not need to return a value
|
Teori C
|
What is WRONG regarding VHDL timing?
|
3) Enough delta delays will add up to one standard time unit
|
Theory D
|
What is the SDF file format used for?
|
1) Describe delays on the gates of a netlist
|
Exercise Code A
source file: INL3_KA.vhdl Name of the source file
Entity: INL3_KA Name of the entity
architecture: KA Name of the architecture
Inputs: A data in, bit
Generic: Del generic, time, default value 2 ns
Outputs: Y data out, bit
Behaviour: Create a inverter with output delay defined by generic Del.
The delay should filter out any pulse shorter than Del.
The generic Del should have a default value of 2 ns if
it is not defined.
Example: Del=4ns, Y=1, A=0, at t=15 ns change A=1 => Y=0 from t=19 ns.
Del=5ns, Y=0, A=1, at t=25 ns change A=0, at t=27 A=1 => Y=0 all the time
Solution
========
entity INL3_KA is
generic (
Del : time := 2 ns
);
port (
A : in bit;
Y : out bit);
end entity;
architecture KA of INL3_KA is
begin
Y <= not A after Del;
end architecture;
Exercise Code B
source file: INL3_KB.vhdl Name of the source file
Entity: INL3_KB Name of the entity
architecture: KB Name of the architecture
Inputs: C data in, bit
R data in, bit
E data in, bit
Outputs: Q data out, std_logic_vector(1 to 3)
Behavour: Create a 3 bit positive edge trigged downcounter with synchronous reset and
output enable. If reset R=1 and a rising edge on C then set internal counter
value to "000". If R=0, and there is a positive (rising) edge on C then
decrement the internal counter value by 1. If E=1 then output the internal
counter value on Q. If E=0 then output ZZZ on Q. Decrementing the minimum value
on the internal counter value will result in the maximum value of the internal
counter value.
Example: R=1, rising edge on C => Q="000"
R=0, Q="100", E=1, rising edge on C => Q="011"
R=0, Q="000", E=1, rising edge on C => Q="111"
R=0, E=0, internal counter value = "110", rising edge on C => Q="ZZZ", internal counter value = "101"
Solution
========
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity INL3_KB is
port (C : in bit;
R : in bit;
E : in bit;
Q : out std_logic_vector(1 to 3));
end entity;
architecture KB of INL3_KB is
begin
process(C)
variable Q_internal : unsigned(1 to 3);
begin
if rising_edge(C) then
if R = '1' then
Q_internal := (others => '0');
else
Q_internal := Q_internal - 1;
end if;
if E = '1' then
Q <= std_logic_vector(Q_internal);
else
Q <= (others => 'Z');
end if;
end if;
end process;
end architecture;
Exercise Code C
source file: INL3_KC.vhdl Name of the source file
Entity: INL3_KC Name of the entity
architecture: KC Name of the architecture
Inputs: C data in, bit
R data in, bit
D data in, bit
Outputs: Q data out, bit
Behaviour: Create an positive edge trigged state machine of moore type with synchronous reset.
The state machine outputs a '1' on Q if the previous input sequence on D has been
"1011". If R='1' and positive edge on C then assume the state machine has not seen
any input bit.
Example: C 0101010101010101010101010101010101010101010101010
R 1111100000000000000000000011000011000000000000000
D 0011001100111100111111001111001100111100000011000
Q -000000000000110000110000001100000000110000000000
Q -000000000000110000110000000000000000000000000000
Solution
========
entity INL3_KC is
port (
C : in bit;
R : in bit;
D : in bit;
Q : out bit);
end entity;
architecture KC of INL3_KC is
signal last_inputs : bit_vector(3 downto 0);
begin
process(C)
begin
if rising_edge(C) then
if R = '1' then
last_inputs <= (others => '0');
else
last_inputs <= last_inputs(2 downto 0) & D;
end if;
end if;
end process;
Q <= '1' when last_inputs = "1011" else '0';
end architecture;
Exercise Code D
source file: INL3_KD.vhdl Name of the source file
Entity: INL3_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(3 downto 0)
B data in, bit_vector(3 downto 0)
C data in, bit_vector(3 downto 0)
Outputs: S data out, bit_vector(5 downto 0)
Behavour: Create a 43-input adder. Assume the inputs are
positive integer numbers. Compute the sum of
A+B+C and return the 6-bit result in S.
Example: A="0101",B="0100",Cin="1001" => S="010010"
A="1100",B="1101",Cin="1110" => S="100111"
Solution
========
library ieee;
use ieee.numeric_bit.all;
entity INL3_KD is
port (A : in bit_vector(3 downto 0);
B : in bit_vector(3 downto 0);
C : in bit_vector(3 downto 0);
S : out bit_vector(5 downto 0));
end entity;
architecture KD of INL3_KD is
begin
S <= bit_vector(unsigned("00" & A) + unsigned("00" & B) + unsigned("00" & C));
end architecture;