| What libraries does not need to be declared (are always availabe)? |
1) None 2) work 3) std 4) work and std |
| What is WRONG regarding subprograms in VHDL? |
1) Procedures can modify its parameters 2) Functions does not need to return a value 3) Functions can not modify its parameters 4) Functions initialize their variables at the start of every function call |
| What is WRONG regarding VHDL timing? |
1) Signal update will always be delayed atleast one delta delay 2) Variable assignments can not contain a delay 3) Enough delta delays will add up to one standard time unit 4) Inertial delay filters out short pulses |
| What is the SDF file format used for? |
1) Describe delays on the gates of a netlist 2) Describe how to program the FPGA 3) Describe where VHDL source files are located in the file system 4) Describe the std_logic datatype |
source file: INL3_KA.vhdl Name of the source file
Entity: INL3_KA Name of the entity
architecture: KA Name of the architecture
Inputs: A data in, bit
Generic: Del generic, time, default value 2 ns
Outputs: Y data out, bit
Behaviour: Create a inverter with output delay defined by generic Del.
The delay should filter out any pulse shorter than Del.
The generic Del should have a default value of 2 ns if
it is not defined.
Example: Del=4ns, Y=1, A=0, at t=15 ns change A=1 => Y=0 from t=19 ns.
Del=5ns, Y=0, A=1, at t=25 ns change A=0, at t=27 A=1 => Y=0 all the time
source file: INL3_KB.vhdl Name of the source file
Entity: INL3_KB Name of the entity
architecture: KB Name of the architecture
Inputs: C data in, bit
R data in, bit
E data in, bit
Outputs: Q data out, std_logic_vector(1 to 3)
Behavour: Create a 3 bit positive edge trigged downcounter with synchronous reset and
output enable. If reset R=1 and a rising edge on C then set internal counter
value to "000". If R=0, and there is a positive (rising) edge on C then
decrement the internal counter value by 1. If E=1 then output the internal
counter value on Q. If E=0 then output ZZZ on Q. Decrementing the minimum value
on the internal counter value will result in the maximum value of the internal
counter value.
Example: R=1, rising edge on C => Q="000"
R=0, Q="100", E=1, rising edge on C => Q="011"
R=0, Q="000", E=1, rising edge on C => Q="111"
R=0, E=0, internal counter value = "110", rising edge on C => Q="ZZZ", internal counter value = "101"
source file: INL3_KC.vhdl Name of the source file
Entity: INL3_KC Name of the entity
architecture: KC Name of the architecture
Inputs: C data in, bit
R data in, bit
D data in, bit
Outputs: Q data out, bit
Behaviour: Create an positive edge trigged state machine of moore type with synchronous reset.
The state machine outputs a '1' on Q if the previous input sequence on D has been
"1011". If R='1' and positive edge on C then assume the state machine has not seen
any input bit.
Example: C 0101010101010101010101010101010101010101010101010
R 1111100000000000000000000011000011000000000000000
D 0011001100111100111111001111001100111100000011000
Q -000000000000110000110000001100000000110000000000
Q -000000000000110000110000000000000000000000000000
source file: INL3_KD.vhdl Name of the source file
Entity: INL3_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(3 downto 0)
B data in, bit_vector(3 downto 0)
C data in, bit_vector(3 downto 0)
Outputs: S data out, bit_vector(5 downto 0)
Behavour: Create a 43-input adder. Assume the inputs are
positive integer numbers. Compute the sum of
A+B+C and return the 6-bit result in S.
Example: A="0101",B="0100",Cin="1001" => S="010010"
A="1100",B="1101",Cin="1110" => S="100111"