TSTE12
Handin exercises 2023 part 2 solutions
Solve the handin tasks individually! No cooperation with anyone else!
Submit all Theory question answers in one submission, using the comment
field of the submission system. Indicate answers using one line per question, indicating
which question (A-D) and which of the multiple choices (1-4) that is your answer to each question.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 on each of theory and code exercises. The handins are
divided into 3 sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 2 is due by Monday 2 October 2023 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Good luck!
Teori A
|
What is WRONG regarding signals in VHDL?
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2) Signals can be defined inside processes
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Theory B
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How many different values are defined in the std_logic datatype?
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3) 9
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Theory C
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Which one is not a predefined signal attribute in the VHDL language?
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3) 'final
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Theory D
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What is WRONG regarding FPGA hardware?
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4) FPGA:s contain a microprocessor running the VHDL code
|
Exercise Code A
source file: INL2_KA.vhdl Name of the source file.
Entity: INL2_KA Name of the entity
architecture: KA Name of the architecture
Inputs: D data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, bit_vector(5 downto 2)
Behaviour: Create a positive edge trigged resettable shift register.
When there is a rising edge on C and R='1' then set Q to
"0000". If there is a rising edge on C and R='0' then
right shift Q one step and put input from D into
leftmost position in Q.
Example: Q="1001", R='1', rising edge on C => Q="0000"
Q="0100", R='0', D='1', rising edge on C => Q="1010"
Solution
========
entity INL2_KA is
port (
D : in bit;
R : in bit;
C : in bit;
Q : out bit_vector(5 downto 2));
end entity;
architecture KA of INL2_KA is
begin
process(C)
variable shiftreg : bit_vector(5 downto 2);
begin
if C'event and (C='1') then
if R='1' then
shiftreg := (others => '0');
else
shiftreg := D & shiftreg(5 downto 3);
end if;
Q <= shiftreg;
end if;
end process;
end architecture;
Exercise Code B
source file: INL2_KB.vhdl Name of the source file
Entity: INL2_KB Name of the entity
architecture: KB Name of the architecture
Inputs: A data in, std_logic
B data in, std_logic
Outputs: Y data out, std_logic
Behavour: Create a 2-input NAND gate where output is '0' or '1' only
if both input uses values '0' or '1' (based on the NAND
function). If any of the inputs have the value 'L' or
'H' beside '0' or '1', then output should be 'L' or 'H'.
If any of the inputs are not '0', '1', 'L', or 'H' then
the output should be 'X'.
Example: A='1', B='0' => Y='1'
A='U', B='1' => Y='X'
A='H', B='1' => Y='L'
Solution
========
library ieee;
use ieee.std_logic_1164.all;
entity INL2_KB is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic);
end entity;
architecture KB of INL2_KB is
signal inputs : std_logic_vector(1 to 2);
begin
inputs <= A & B;
with inputs select
Y <= '0' when "11",
'1' when "00" | "01" | "10",
'L' when "H1" | "1H" | "HH",
'H' when "L0" | "0L" | "LL" |
"L1" | "0H" | "LH" |
"H0" | "1L" | "HL",
'X' when others;
end architecture;
Exercise Code C
source file: INL2_KC.vhdl Name of the source file
Entity: INL2_KC Name of the entity
architecture: KC Name of the architecture
Inputs: D data in, bit_vector(2 to 3)
C data in, bit
S data in, bit
Outputs: Q data out, bit_vector(2 to 3)
Behavour: Create a 2-bit positive edge triggered register
with asynchronous set. If S='1' then set Q to "11".
If there is a rising edge on C and S='0' then copy
the value on D to Q.
Example: S='1' => Q="11"
S='0', D="01", rising edge on C => Q="01"
Solution
========
entity INL2_KC is
port (
D : in bit_vector(2 to 3);
C : in bit;
S : in bit;
Q : out bit_vector(2 to 3));
end entity;
architecture KC of INL2_KC is
begin
process(C,S)
begin
if S='1' then
Q <= "11";
elsif C'event and C='1' then
Q <= D;
end if;
end process;
end architecture;
Exercise Code D
source file: INL2_KD.vhdl Name of the source file
Entity: INL2_KD Name of the entity
architecture: KD Name of the architecture
Inputs: C data in, bit
E data in, bit
R data in, bit
Outputs: Q data out, bit_vector(3 downto 1)
Behaviour: Create a negative edge triggered 3 bit counter with
synchronous reset and enable input. If falling edge
on C and R='1' then Q="000". If a falling edge on C,
R='0' and E='1' then increment Q by 1. Incrementing
"111" generates "000".
Example: R='0',Q="010",E='0',falling edge on C => Q="010"
R='1', falling edge on C => Q="000"
R='0',Q="110",E='1',falling edge on C => Q="111"
Solution
========
library ieee;
use ieee.numeric_bit.all;
entity INL2_KD is
port (
C : in bit;
E : in bit;
R : in bit;
Q : out bit_vector(3 downto 1));
end entity;
architecture KD of INL2_KD is
begin
process(C)
variable count : unsigned(3 downto 1);
begin
if C'event and C='0' then
if R='1' then
count := "000";
elsif E='1' then
count := count+1;
end if;
Q <= bit_vector(count);
end if;
end process;
end architecture;