What is WRONG regarding signals in VHDL? |
1) Signals can be assigned values from variables 2) Signals can be defined inside processes 3) Entity ports are signals 4) Signals are always assigned a value at simulation start |
How many different values are defined in the std_logic datatype? |
1) 2 2) 4 3) 9 4) 12 |
Which one is not a predefined signal attribute in the VHDL language? |
1) 'delayed 2) 'event 3) 'final 4) 'stable |
What is WRONG regarding FPGA hardware? |
1) FPGA:s can contain dedicated RAM blocks 2) FPGA:s often support multiple I/O standards 3) FPGA:s often include dedicated multipliers 4) FPGA:s contain a microprocessor running the VHDL code |
source file: INL2_KA.vhdl Name of the source file. Entity: INL2_KA Name of the entity architecture: KA Name of the architecture Inputs: D data in, bit R data in, bit C data in, bit Outputs: Q data out, bit_vector(5 downto 2) Behaviour: Create a positive edge trigged resettable shift register. When there is a rising edge on C and R='1' then set Q to "0000". If there is a rising edge on C and R='0' then right shift Q one step and put input from D into leftmost position in Q. Example: Q="1001", R='1', rising edge on C => Q="0000" Q="0100", R='0', D='1', rising edge on C => Q="1010"
source file: INL2_KB.vhdl Name of the source file Entity: INL2_KB Name of the entity architecture: KB Name of the architecture Inputs: A data in, std_logic B data in, std_logic Outputs: Y data out, std_logic Behavour: Create a 2-input NAND gate where output is '0' or '1' only if both input uses values '0' or '1' (based on the NAND function). If any of the inputs have the value 'L' or 'H' beside '0' or '1', then output should be 'L' or 'H'. If any of the inputs are not '0', '1', 'L', or 'H' then the output should be 'X'. Example: A='1', B='0' => Y='1' A='U', B='1' => Y='X' A='H', B='1' => Y='L'
source file: INL2_KC.vhdl Name of the source file Entity: INL2_KC Name of the entity architecture: KC Name of the architecture Inputs: D data in, bit_vector(2 to 3) C data in, bit S data in, bit Outputs: Q data out, bit_vector(2 to 3) Behavour: Create a 2-bit positive edge triggered register with asynchronous set. If S='1' then set Q to "11". If there is a rising edge on C and S='0' then copy the value on D to Q. Example: S='1' => Q="11" S='0', D="01", rising edge on C => Q="01"
source file: INL2_KD.vhdl Name of the source file Entity: INL2_KD Name of the entity architecture: KD Name of the architecture Inputs: C data in, bit E data in, bit R data in, bit Outputs: Q data out, bit_vector(3 downto 1) Behaviour: Create a negative edge triggered 3 bit counter with synchronous reset and enable input. If falling edge on C and R='1' then Q="000". If a falling edge on C, R='0' and E='1' then increment Q by 1. Incrementing "111" generates "000". Example: R='0',Q="010",E='0',falling edge on C => Q="010" R='1', falling edge on C => Q="000" R='0',Q="110",E='1',falling edge on C => Q="111"