TSTE12
Handin exercises 2023 part 1 solutions
IMPORTANT: Handin tasks are INDIVIDUAL. Do NOT work together to solve
these questions!
Theory questions are submitted in LISAM in similar
way to the coding submission.
Submit all theory question answers in one submission. Indicate answers
using one line per question, indicating which question (A-D) and which of the
multiple choices (1-4) that is your answer to each question.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 on each of theory and code exercises. The handins are
divided into 3 sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercise answers must be submitted at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 1 is due by Monday 18 September 2022 at 23.30!
The results will be available in the lisam submission.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Good luck!
Theory A
|
Which datatype was NOT part of the original VHDL standard from 1987?
|
3) std_logic
|
Theory B
|
How many architectures can be created for one entity?
|
4) no upper limit defined
|
Teori C
|
What is WRONG regarding assignments in VHDL?
|
2) Signals can not be assigned a value from a variable
|
Theory D
|
What is WRONG related to VHDL?
|
3) The language is object-oriented (i.e. support inheritance)
|
Exercise Code A
source file: INL1_KA.vhdl Name of the source file
Entity: INL1_KA Name of the entity
architecture: KA Name of the architecture
Inputs: A data in, bit
B data in, bit
C data in, bit
Outputs: Y data out, bit
Behavour: Create a 3-input NOR gate.
Example: A='0',B='0',C='0' => Y='1'
A='1',B='0',C='1' => Y='0'
Solution
========
entity INL1_KA is
port (
A : in bit;
B : in bit;
C : in bit;
Y : out bit);
end entity;
architecture KA of INL1_KA is
begin
Y <= not (A or B or C);
end architecture;
Exercise Code B
source file: INL1_KB.vhdl Name of the source file
Entity: INL1_KB Name of the entity
architecture: KB Name of the architecture
Inputs: A data in, bit
B data in, bit
C data in, bit
Outputs: Y data out, bit
Behavour: Create a 3-input OR gate with a 3 ns output delay.
Any output pulse shorter than 3 ns should be filtered
out.
Example: A='0', B='1', C='0' for a long time => Y='1'
A='0', B='1', C='0', B change to '0' at time 2 ns, C='1' at 4 ns => Y='1' (no change)
A='0', B='0', C='1', B change to '0' at time 6 ns => Y='0' from time 9 ns
Solution
========
entity INL1_KB is
port (
A : in bit;
B : in bit;
C : in bit;
Y : out bit);
end entity;
architecture KB of INL1_KB is
begin
Y <= (A or B or C) after 3 ns;
end architecture;
Exercise Code C
source file: INL1_KC.vhdl Name of the source file
Entity: INL1_KC Name of the entity
architecture: KC Name of the architecture
Inputs: A data in, bit_vector(0 to 2)
Outputs: Y data out, bit
Behaviour: Output a '1' if 2 or 3 elements in A are '1', output '0' otherwise
Example: A="010" => Y='0'
A="110" => Y='1'
Solution
========
entity INL1_KC is
port (
A : in bit_vector(0 to 2);
Y : out bit);
end entity;
architecture KC of INL1_KC is
begin
Y <= (A(0) and A(1)) or (A(0) and A(2)) or (A(1) and A(2));
end architecture;
Exercise Code D
source file: INL1_KD.vhdl Name of the source file.
Entity: INL1_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(0 to 3)
B data in, bit_vector(1 downto 0)
Outputs: Y data out, bit
Behaviour: Create a multiplexer where B selects which element in A
to output on Y. B is decoded as an unsigned 2-bit value
and used as index into A.
Example: A="0100",B="01" => Y='1'
A="1010"'B="11" => Y='0'
Solution
========
entity INL1_KD is
port (
A : in bit_vector(0 to 3);
B : in bit_vector(1 downto 0);
Y : out bit);
end entity;
architecture KD of INL1_KD is
begin
with B select
Y <= A(0) when "00",
A(1) when "01",
A(2) when "10",
A(3) when others;
end architecture;