Department of Electrical Engineering

Lectures TSEA44

Lectures 2022

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog/Systemverilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding. Lab2
5. Slides. Guest Lecture from AXIS Communications, test and verification
6. Slides. Designing for FPGAs.
7. Slides. DMA, Lab3, testbenches
8. Slides. Memories. Custom Instruction. Lab 4

Lectures 2019

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog/Systemverilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding.
5. Slides. Lab2, Trouble shooting FPGA designs. Clock domain crossings.
6. Slides. Designing for FPGAs.
7. Slides. DMA, Lab3, testbenches
8. Slides. Memories. Custom Instruction. Lab 4

Lectures 2018

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog/Systemverilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding.
5. Slides, Lab2, Trouble shooting FPGA designs. Clock domain crossings.
6. Slides. Designing for FPGAs.
7. Slides. DMA, Lab3, testbenches
8. Slides. Memories. Custom Instruction. Lab 4

Lectures 2017

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog/Systemverilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding. (Lab2).
5. Slides. Lab2, Trouble shooting FPGA designs. Clock domain crossings. Guest Lecture from ARM Sweden AB
6. Slides. Designing for FPGAs.
7. Slides. DMA, Lab3, testbenches
8. Slides. Memories. Custom Instruction. Lab 4

Lectures 2016

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding. (Lab2).
5. Slides. Lab2, Trouble shooting FPGA designs. Clock domain crossings. Guest Lecture from ARM Sweden AB
6. Slides. Designing for FPGAs.
7. Slides. DMA, Lab3, testbenches
8. Slides. Memories. Custom Instruction. Lab 4

Lectures 2015

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog. Lab 0. The SystemVerilog example I showed during the lecture: squarewave.sv tb.sv
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. The lab system, hardware acceleration. JPEG encoding. Lab2.
5. Slides. Trouble shooting FPGA designs. Clock domain crossings.
6. Slides. Designing for FPGAs. (preliminary)
7. Slides. DMA. Lab3. (preliminary)
8. Slides. Memories. Custom Instruction. Lab 4 (preliminary)

Lectures 2014

1. Slides. Course introduction. Soft computers. FPGAs
2. Slides. Introduction to Verilog. Lab 0.
3. Slides. OR1200. Instruction Set. Architecture. Lab1. Pipelining
4. Slides. Hardware acceleration. JPEG. Lab2.
5. Slides. Pipeling, Cache and Testbench.
6. Slides. Design for FPGA. Trouble shooting. Andreas Ehliar
7. Slides. DMA. Lab3.
8. Slides. Memories. Custom Instruction. Lab 4