----------------------------------------------------------------------
-- Project:  TSEA22 LAB-4
-- File:     lab4-exempelkod.txt
-- Author:   Olov Andersson
-- Date:     2017-04-18
-- Revision: 2.1
-- Target:   XC9572
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity vga is
    Port ( clk : in std_logic;
           hsync, vsync : out std_logic;
           px_r, px_g, px_b : out std_logic);
end vga;

architecture avga of vga is
  signal bild_slack, seg_1, x_wrap, y_wrap : std_logic;
  signal x_rak, y_rak : unsigned(9 downto 0);

  signal sprite_x : unsigned(9 downto 0);
  signal size_x, size_y : unsigned(3 downto 0);
  signal sprite, sprite_x_true, sprite_y_true : std_logic;

attribute keep : string;

attribute keep of sprite : signal is "TRUE";


begin
  process(clk)
  begin
    if rising_edge(clk) then
      if (x_wrap = '1') then
        x_rak <= "0000000000";
      else
        x_rak <= x_rak + 1;
      end if;
    end if;
  end process;
  x_wrap <= '1' when (x_rak = 793) else '0';

  process(clk)
  begin
    if rising_edge(clk) then
      if (y_wrap = '1') then
        y_rak <= "0000000000";
      elsif (x_wrap = '1') then
        y_rak <= y_rak + 1;
      end if;
    end if;
  end process;
  y_wrap <= '1' when ((y_rak = 523) and (x_wrap = '1')) else '0';

  bild_slack <= '1' when (x_rak >= 640) or (y_rak >= 480) else '0';
  hsync <= '0' when (x_rak >= 653) and (x_rak <= 746) else '1';
  vsync <= '0' when (y_rak >= 490) and (y_rak <=491) else '1';
----------------------------------------------------------------------
  seg_1 <= '1' when (x_rak >= 200) and (x_rak <= 250) and
		 (y_rak >= 260) and (y_rak <= 460) else '0';


  px_r <= '0' when (bild_slack = '1') or (seg_1 = '0') else '1';
  px_g <= '0' when (bild_slack = '1') or (seg_1 = '0') else '1';
  px_b <= '0' when (bild_slack = '1') or (seg_1 = '0') else '1';

--####################################################################

  process(clk)

  begin
    if rising_edge(clk) then
      if (sprite_x = 633) then
        sprite_x <= "0000000000";

      elsif (y_wrap = '1') then
        sprite_x <= sprite_x + 1;

      end if;

    end if;

  end process;



  process(clk)

  begin
    if rising_edge(clk) then
      if size_x = 7 then

        size_x <= "0000";

      elsif ((x_rak = sprite_x) or (sprite_x_true = '1')) then
        size_x <= size_x + 1;

      end if;

    end if;

  end process;


  process(clk)

  begin
    if rising_edge(clk) then
      if (x_wrap = '1') and (size_y = 11) then
        size_y <= "0000";

      elsif (x_wrap = '1') and ((y_rak = 150) or (sprite_y_true = '1')) then

        size_y <= size_y + 1;
      end if;
    end if;

  end process;


  sprite_x_true <= '1' when (size_x /= 0) else '0';
  sprite_y_true <= '1' when (size_y /= 0) else '0';
  sprite <= sprite_x_true and sprite_y_true;

end avga;