| What is wrong related to signals in VHDL? |
1) Signal value updates are always delayed 2) Signals are always initilized at simulation start 3) Signals can be assigned values from variables 4) Signals can be declared in the declaration area of a processes |
| What is wrong regarding VHDL timing? |
1) Variable are always updated immediately 2) Delta delays will add up to a standard delay 3) Signal updates are always delayed 4) Processes can contain wait statements |
| What is the maximum number of different architectures connect to an entity declaration? |
1) 1 2) 2 3) 16 4) not defined |
| What is wrong related to variables? |
1) Variables are always initialized 2) Variable declarations does not include the type 3) Variables can be declared in functions 4) Variables can be assigned to the value of a constant |
| What is wrong regarding processes? |
1) Processes can be assigned a label 2) A process is required to have a sensitivity list 3) Procedures can be declared in a process 4) The process contains sequential code |
| What is not a valid VHDL identifier (VHDL standard 1987 version)? |
1) SN74LS00 2) One_fine_design 3) register 4) MC68000 |
| What is wrong related to the VHDL language? |
1) Data types are automatically translated to match the variable data type 2) Packages are used to support information hiding 3) Operators can be redefined (overloading) 4) Inheritence is not supported |
| What is wrong regarding VHDL synthesis? |
1) Tristate busses can not be synthesized
2) For and loop statements in a process can not be synthesized 3) Only a subset of the language can be synthesized 4) Fixed delays in signal assignments are ignored by synthesis tools |
| What wrong related to FPGA hardware? |
1) FPGA hardware often include dedicated memory 1) The synthesis output is executed by a processor in the FPGA chip 2) An FPGA can use a different clock frequency internally 3) RAM based FPGAs must be configured every time power is applied |
source file: INL5_KA.vhdl Name of the source file.
Entity: INL5_KA Name of the entity
Architecture: KA Name of the architecture
Inputs: A data in, bit_vector(5 downto 3)
Outputs: Y data out, bit
Behavour: Create a 3-input NAND-gate.
Example: A="010" => Y='1',
A="111" => Y='0',
A="011" => Y='1'
source file: INL5_KB.vhdl Name of the source file.
Entity: INL5_KB Name of the entity
Architecture: KB Name of the architecture
Inputs: A data in, bit
Delay generic, time, default value 5 ns
Outputs: Y data out, bit
Behavour: An inverter with configurable delay.
Output inverse of A after time Delay.
Example: A='1',Y='0',Delay=3ns, A='0' at time 12 ns => Y='1' at time 15 ns
source file: INL5_KC.vhdl Name of the source file.
Package: INL5_KC Name of the package
Function: KC Name of the function
Inputs: A data in, bit_vector unconstrained range
B data in, bit
Outputs: data out, integer
Behavour: Create a packet containing a function KC that count how
many time the value B is found in the vector A and return
that value.
Examples: A="0010", B='1' => KC(A,B)=1
A="110101", B='0' = KC(A,B)=2
source file: INL5_KD.vhdl Name of the source file.
Entity: INL5_KD Name of the entity
Architecture: KD Name of the architecture
Inputs: A data in, std_logic
B data in, std_logic
Out: Y data out, std_logic
Behaviour: 2-input NAND-gate. An input of '0' or 'L' are seen as the
logic level 0, and the input values '1' and 'H' are seen
as the logic level 1. If any of the inputs have a value not
in the set '0','1','L','H' then output 'X', otherwise output the
corresponding logic level.
Example: A='W',B='0' => Y='X'
A='H',B='1' => Y='0'
A='0',B='0' => Y='1'
A='H',B='L' => Y='1'
source file: INL5_KE.vhdl Name of the source file.
Entity: INL5_KE Name of the entity
Architecture: KE Name of the architecture
Inputs: D data in, bit_vector(4 downto 2)
R data in, bit
C data in, bit
Outputs: Q data out, bit_vector(4 downto 2)
Behavour: A positive edge trigged 3-bit register with synchronous reset.
If a rising edge on C and R = '1' then Q = "000". If a rising
edge on C and R = '0' then copy the value from D to Q.
Example: Rising edge on C, R='0' and D="011" => Q="011"
Rising edge on C, R='1' => Q="000"
source file: INL5_KF.vhdl Name of the source file.
Entity: INL5_KF Name of the entity
Architecture: KF Name of the architecture
Inputs: C data in, bit
L data in, bit
D data in, bit_vector(2 downto 0)
Outputs: Q data out, bit_vector(2 downto 0)
Behavour: Synchronous positive edge trigged binary downcounter with
asynchronous load. If L='1' then copy D to Q. If L='0'
and positive edge on C then decrement the binary value of Q.
Q="111" is decremented to "000"Q="000" is
decremented to "111".
Example: L='1', D="101" => Q="101"
L='0', positive edge on C, Q="010" => Q="001"
L='0', positive edge on C, Q="111" => Q="000"
L='0', positive edge on C, Q="000" => Q="111"
source file: INL5_KG.vhdl Name of the source file.
Entity: INL5_KG Name of the entity
Architecture: KG Name of the architecture
Inputs: D data in, bit
C data in, bit
Outputs: Q data out, bit_vector(1 to 3)
Behavour: A negative edge trigged shift register. If negative edge on
C then shift register to the right, and put value of D on the
leftmost position of the register.
Example: D='1', negative edge on C, Q="000" => Q="100"
D='0', negative edge on C, Q="101" => Q="010"
source file: INL5_KH.vhdl Name of the source file.
Entity: INL5_KH Name of the entity
Architecture: KH Name of the architecture
Inputs: A data in, bit
B data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, bit
Behavour: Positive edge trigged state machine of Mealy type with asynchronous
reset input. The state machine should output a ''0' when the
current input have A=B and A != B in the previous two clock cycles.
If R='1' then set Q='0', and assume A=B in previous clock cycle.
Example: (assume here these are in a sequence)
R='1',A='0',B='1' => Q='0'
R='1',A='0',B='0' => Q='0'
R='0',A='1',B='0' rising edge on C => Q='0'
R='0',A='0',B='0' rising edge on C => Q='0'
R='0',A='1',B='0' rising edge on C => Q='0'
R='0',A='0',B='1' rising edge on C => Q='0'
R='0',A='0',B='1' => Q='0'
R='0',A='0',B='0' => Q='1'
R='0',A='1',B='0' rising edge on C => Q='0'
R='0',A='1',B='1' => Q='0'
source file: INL5_KJ.vhdl Name of the source file.
Entity: INL5_KJ Name of the entity
Architecture: KJ Name of the architecture
Inputs: A data in, bit_vector(3 downto 1)
Outputs: Y data out, bit
Behavour: Instanciate the component work.INL5_KJ_test(behav) into the
design. The component will have the same inputs and outputs as
INL5_KJ. The input A should have bit index 2 inverted before
it is connected to input A INL5_KJ_test. The Y output from
INL5_KJ_test connects to the Y output of INL5_KJ.
Example: Assume INL5_KJ_test calculates the OR function between A and B:
A = "010" => Y='0'
A="000" => Y='1'