| What is WRONG related to VHDL? |
1) Arrays must use integer values as indexes 2) Overloading (defining new function for existing builtin operators) is supported 3) Time is a predefined data type in VHDL 4) File I/O is supported. |
| Which is not an HDL (Hardware Description Language)? |
1) SystemVerilog 2) Ada 3) Verilog 4) System-C |
| What is WRONG related to processes in VHDL? |
1) Proceses can have both wait statements and a non-empty sensitivity list 2) Data types can be defined inside a process 3) Variables in processes keep their values when the process restarts 4) Processes without a sensitivity list will be restarted immediately |
| What is NOT a valid identifier in VHDL'87? |
1) bus_nr_9 2) SN74LS00 3) register 4) A_very_long_name |
source file: INL4_KA.vhdl Name of the source file
Entity: INL4_KA Name of the entity
architecture: KA Name of the architecture
Inputs: E data in, bit
R data in, bit
C data in, bit
Outputs: Q data out, std_logic_vector(2 downto 0)
Behaviour: Create a positive edge (rising edge) clocked counter with asynchronous
reset R and count enable E that counts with step size 3. If R = '1' then
output Q = "000". If a rising edge on C and R='0' and E='1'
then increment the Q value by 3. Incrementing "111" by 3 => "010",
incrementing "110" by 3 => "001", incrementing "101" by 3 => "000".
Example: Q="101", R='0', E='1', rising edge on C => Q = "000"
Q="100", R='1', => Q = "000"
Q="010", R='0', E='1', rising edge on C => Q = "101"
Q="001", R='0', E='0', rising edge on C => Q = "001"
source file: INL4_KB.vhdl Name of the source file
Package: INL4_KB Name of the package
function: KB Name of the function
Inputs: A data in, signal, bit_vector (unconstrained size)
Outputs: data out, bit
Behaviour: Create a package with a function KB that determines if the
number of 1:s in A is odd or even. Return 0 if the number of
ones in A is even, return 1 if the number of ones in A is odd.
Example: A="0011" => KB(A)='0'
A="111" => KB(A)='1'
A="1101" => KB(A)='1'
A="0" => KB(A)='0'
source file: INL4_KC.vhdl Name of the source file
Entity: INL4_KC Name of the entity
architecture: KC Name of the architecture
Inputs: A data in, bit_vector(1 to 8)
Outputs: Y data out, bit
Behavour: Create a gate that outputs a '1' if there are 5 or more bits
in A that are '1'.
Example: A="11000111" => Y = '1'
A="11010111" => Y = '1'
A="10101010" => Y = '0'
A="01000100" => Y = '0'
source file: INL4_KD.vhdl Name of the source file
Entity: INL4_KD Name of the entity
architecture: KD Name of the architecture
Inputs: A data in, bit_vector(1 downto 0)
B data in, bit
Outputs: Y data out, bit
Behaviour: Create a detector that when B have a positive edge checks if A has changed
during the previous 20 ns. If A did change then output '1' while
B is '1', else output '0'. Output '0' when B is '0'.
Example: A="11", B='0' for 300 ns. Y=0. B change to '1' => Y still '0'
A="01", B='0' for 200 ns, A="11" for 10 ns, B change to '1' => Y = '1' while B='1'
B='0' => Y='0'