TSTE12
Handin exercises 2024 part 3 solutions
Solve the handin tasks individually! No cooperation with anyone else!
Theory questions are submitted in LISAM using the comment field.
To pass on the handin exercises it is required to reach 9 correct
exercises of 12 on each of theory and code exercises. The handins are
divided into 3 sets of questions with 4 points of theori and 4 points
of coding on each.
Read closely the instructions on the handin main page!
Note the time schedule!
Handin exercises must be in place at latest by the deadline on the
given date. Use the commands "module load courses/TSTE12 ; TSTE12handin" to
open a shell window to work from.
Handin part 3 is due by Monday 21 October 2024 at 23.30!
The results will be available in the lisam course room.
Note:
Read the instructions at the main page!!
Ask if any difficulties or uncertainty!!
Solve the tasks individually!!
Good luck!
Theory A
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What is WRONG related to the VHDL language?
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1) VHDL is the only hardware description language available
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Theory B
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What is WRONG regarding subprograms in VHDL?
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3) Functions can modify their parameters
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Teori C
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What is WRONG regarding VHDL timing?
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2) Variable assignments can contain a delay
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Theory D
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What is the VITAL standard used for?
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4) Describe how gate level simulation models should be described
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Exercise Code A
source file: INL3_KA.vhdl Name of the source file
Entity: INL3_KA Name of the entity
architecture: KA Name of the architecture
Inputs: A data in, bit_vector(3 downto 0)
B data in, bit_vector(3 downto 0)
C data in, bit
Outputs: S data out, bit_vector(4 downto 0)
Behavour: Create a 2-input adder with a carry input. Assume the
inputs are positive integer numbers. Compute the
sum A+B+C and return the 5 bit result in S.
Example: A="0101",B="0100",C='1' => S="01010"
A="1100",B="1101",C='0' => S="11001"
A="1000",B="0000",C='1' => S="01001"
Solution
========
library ieee;
use ieee.numeric_bit.all;
entity INL3_KA is
port (
A, B : in bit_vector(3 downto 0);
C : in bit;
S : out bit_vector(4 downto 0));
end entity;
architecture KA of INL3_KA is
begin
S <= bit_vector(unsigned('0' & A) + unsigned('0' & B) + unsigned("0000" & C));
end architecture;
Exercise Code B
source file: INL3_KB.vhdl Name of the source file
Entity: INL3_KB Name of the entity
architecture: KB Name of the architecture
Inputs: A data in, bit
B data in, bit
Generic: Del generic, time, default value 2 ns
Outputs: Y data out, bit
Behaviour: Create an AND-gate with output delay defined by the generic Del.
The delay should filter out any output pulse shorter than Del.
The generic Del should have a default value of 2 ns if
it is not defined.
Example: Del=4ns, Y=0, A=0, B='1', at t=15 ns change A=1 => Y=1 from t=19 ns.
Del=5ns, Y=1, A=1, B='1', at t=25 ns change B=0, at t=27 B=1 => Y=1 all the time
Solution
========
entity INL3_KB is
generic (
Del : time := 2 ns);
port (
A, B : in bit;
Y : out bit);
end entity;
architecture KB of INL3_KB is
begin
Y <= A and B after Del;
end architecture;
Exercise Code C
source file: INL3_KC.vhdl Name of the source file
Entity: INL3_KC Name of the entity
architecture: KC Name of the architecture
Inputs: C data in, bit
D data in, bit_vector(1 to 4)
L data in, bit
E data in, bit
Outputs: Q data out, bit_vector(1 to 4)
Behavour: Create a 4 bit positive edge trigged loadable downcounter with enable.
If E='0' then nothing changes in the counter. If E='1', rising edge on C
and L='0' then the value of Q is decremented by 1. If E='1', rising edge
on C and L='1' then the new value of Q is the value of D. Decrementing the
minimal value results in the maximum value being output.
Example: E='1',L='1',D="0110", rising edge on C => Q="0110"
E='0',Q="1010", rising edge on C => Q="1010"
E='1',L='0',Q="0000", rising edge on C => Q="1111"
E='1',L='0',Q="0011", rising edge on C => Q="0010"
Solution
========
library ieee;
use ieee.numeric_bit.all;
entity INL3_KC is
port (
C : in bit;
D : in bit_vector(1 to 4);
L : in bit;
E : in bit;
Q : out bit_vector(1 to 4));
end entity;
architecture KC of INL3_KC is
begin
process(C)
variable CountValue : unsigned(1 to 4);
begin
if C='1' and C'event then
if E='1' then
if L='1' then
CountValue := unsigned(D);
else
CountValue := CountValue - 1;
end if;
end if;
end if;
Q <= bit_vector(CountValue);
end process;
end architecture;
Exercise Code D
source file: INL3_KD.vhdl Name of the source file
Entity: INL3_KD Name of the entity
architecture: KD Name of the architecture
Inputs: C data in, bit
R data in, bit
A data in, bit
B data in, bit
Outputs: Q data out, bit
Behaviour: Create an positive edge trigged state machine of moore type with synchronous reset.
The state machine outputs a '1' on Q if the previous 3 clock cycles have had inputs
where A=B in each clock cycle. If R='1' and positive edge on C then the state machine
will assume no prior input has had A=B.
Example: C 0101010101010101010101010101010101010101010101010
R 1111000000000000000000000000001100001100000000000
A 0011001100111100111111001111001100111100001100110
B 1100111100111111111111000011001100110011001100000
Q 0000000000011110000001111000000000000000000001100
Solution
========
entity INL3_KD is
port (
C : in bit;
R : in bit;
A : in bit;
B : in bit;
Q : out bit);
end entity;
architecture KD of INL3_KD is
begin
process(C)
variable old_eq : boolean;
variable old_old_eq : boolean;
begin
if C='1' and C'event then
if R='1' then
old_eq := false;
old_old_eq := false;
Q <= '0';
else
if (A = B) and old_eq and old_old_eq then
Q <= '1';
else
Q <= '0';
end if;
old_old_eq := old_eq;
old_eq := A = B;
end if;
end if;
end process;
end architecture;