| What is WRONG related to the VHDL language? |
1) VHDL is the only hardware description language available 2) VHDL is object based, not object oriented 3) VHDL is standardized by IEEE 4) VHDL support concurrent operations |
| What is WRONG regarding subprograms in VHDL? |
1) Procedures can modify its parameters 2) Functions must to return a value 3) Functions can modify their parameters 4) Functions initialize their variables at the start of every function call |
| What is WRONG regarding VHDL timing? |
1) Signal update will always be delayed atleast one delta delay 2) Variable assignments can contain a delay 3) Delta delays does not affect the current standard time value 4) Inertial delay filters out short puls assignments |
| What is the VITAL standard used for? |
1) Describe what parts of the VHDL language that can be synthesized 2) Describe how to program the FPGA 3) Describe where VHDL source files are located in the file system 4) Describe how gate level simulation models should be described |
source file: INL3_KA.vhdl Name of the source file
Entity: INL3_KA Name of the entity
architecture: KA Name of the architecture
Inputs: A data in, bit_vector(3 downto 0)
B data in, bit_vector(3 downto 0)
C data in, bit
Outputs: S data out, bit_vector(4 downto 0)
Behavour: Create a 2-input adder with a carry input. Assume the
inputs are positive integer numbers. Compute the
sum A+B+C and return the 5 bit result in S.
Example: A="0101",B="0100",C='1' => S="01010"
A="1100",B="1101",C='0' => S="11001"
A="1000",B="0000",C='1' => S="01001"
source file: INL3_KB.vhdl Name of the source file
Entity: INL3_KB Name of the entity
architecture: KB Name of the architecture
Inputs: A data in, bit
B data in, bit
Generic: Del generic, time, default value 2 ns
Outputs: Y data out, bit
Behaviour: Create an AND-gate with output delay defined by the generic Del.
The delay should filter out any output pulse shorter than Del.
The generic Del should have a default value of 2 ns if
it is not defined.
Example: Del=4ns, Y=0, A=0, B='1', at t=15 ns change A=1 => Y=1 from t=19 ns.
Del=5ns, Y=1, A=1, B='1', at t=25 ns change B=0, at t=27 B=1 => Y=1 all the time
source file: INL3_KC.vhdl Name of the source file
Entity: INL3_KC Name of the entity
architecture: KC Name of the architecture
Inputs: C data in, bit
D data in, bit_vector(1 to 4)
L data in, bit
E data in, bit
Outputs: Q data out, bit_vector(1 to 4)
Behavour: Create a 4 bit positive edge trigged loadable downcounter with enable.
If E='0' then nothing changes in the counter. If E='1', rising edge on C
and L='0' then the value of Q is decremented by 1. If E='1', rising edge
on C and L='1' then the new value of Q is the value of D. Decrementing the
minimal value results in the maximum value being output.
Example: E='1',L='1',D="0110", rising edge on C => Q="0110"
E='0',Q="1010", rising edge on C => Q="1010"
E='1',L='0',Q="0000", rising edge on C => Q="1111"
E='1',L='0',Q="0011", rising edge on C => Q="0010"
source file: INL3_KD.vhdl Name of the source file
Entity: INL3_KD Name of the entity
architecture: KD Name of the architecture
Inputs: C data in, bit
R data in, bit
A data in, bit
B data in, bit
Outputs: Q data out, bit
Behaviour: Create an positive edge trigged state machine of moore type with synchronous reset.
The state machine outputs a '1' on Q if the previous 3 clock cycles have had inputs
where A=B in each clock cycle. If R='1' and positive edge on C then the state machine
will assume no prior input has had A=B.
Example: C 0101010101010101010101010101010101010101010101010
R 1111000000000000000000000000001100001100000000000
A 0011001100111100111111001111001100111100001100110
B 1100111100111111111111000011001100110011001100000
Q 0000000000011110000001111000000000000000000001100