Department of Electrical Engineering
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TSTE08 - Analog and discrete-time integrated circuits

Laboratories and projects

The course includes a mandatory project part. (Essentially the written examination of the laboratory part). The project consists of

  • designing an operational transconductance amplifier in the Cadence design flow and then use it in a switched-capacitor accumulator and a switched-capacitor filter. You should be able to characterize the effects of your non-ideal amplifier in a slightly larger system and understand the limitations to the system.
    See more at the following path (which will be updated during the beginning of the 2020 version of the course):
    /site/edu/es/ANTIK/antikLab/doc/ANTIK_0008_LM_atikLab*

Project

The CMOS part of the course has the following labs (notice that these labs do not require obligatory attendance! The labs are taken together with TSEI12)

  • Lab 0: Introduction to the cadence simulator environment
  • Lab 1: ANTIK_0006_LM_atikLabOta
  • Lab 2: ANTIK_0007_LM_atikLabScAcc
  • Lab 3: ANTIK_0008_LM_atikLabScFilter
  • Lab 4: Wrap-up

Notice that

  • The laboratory work is done in groups of three students.
  • The first three sessions are not obligatory attendance
  • Prepare yourselves before you go to the lab and some of the exercises in the Exercise manual should be solved prior to the laboratory work.
  • The labs are performed and eventually a project report is handed in to the examiner in May (latest). See more below!

Deadline and examination

Last Thursday of May is the last day for sending in the report in order to get it marked before the Summer. It is however encouraged to hand in sooner ... Send the report to the course responsible.

OAThe quality of your written report/project is graded with respect to:

  • Results, do you meet the specification, if not why? Can the specification be met, for example.
  • Report, is it well written, good language, etc.
  • Quality, have you examined "everything"?
  • Motivation, how well have you motivated your design?
The project will be graded Pass or Fail.

Page responsible: J Jacob Wikner
Last updated: 2020-01-14