TSIU03 - System Design
TSIU03 is an introductory course to circuit design using VHDL. The general description of the course can be found in the Study Plan. The course is intended for bachelor students with no previous knowledge in VHDL. Students of the course are supposed to have previous knowledge in switching theory and it is highly recommended to have studied circuit design before. Master students (specially those that have knowledge in circuit design and programming skills) should preferably apply for the more advanced course Design of Digital Systems (TSTE12). Due to a partial overlap between the content in TSIU03 and TSTE12, it is only allowed to register for one of these courses.
Credits: 8 ECTS
For more information, read the Course Description document.
Registration for the course: Studieportalen.
Mario Garrido: Course responsible.
Olov Andersson: Labs, Project and Assignments.
Peter Johansson: Labs and Project.
Kent Palmkvist: Labs.
Erik Bertilsson: Labs.
Narges Mohammadi: Labs.
Kristoffer Jäsperi: Labs.
"VHDL for Logic Synthesis", Andrew Rushton. John Wiley & Sons, 2011 (3rd edition). ISBN-13: 978-0470688472. Links: LIU Library, Online Version.
"Digital Design: An Embedded Systems Approach Using VHDL", Peter J. Ashenden. Morgan Kaufmann, 2007. ISBN-13: 978-0123695284. Links: LIU Library, Online Version.
You can download the lectures here. I recommend that you go through the lectures and try to solve the questions again. You can ask any doubt to the teachers.
You can download the laboratories here. The laboratories will be uploaded to the web page before the corresponding laboratory session, so that you can start and work on them whenever you want.
- Important documents for the project:
- Project Specification
- Guidelines to Write the Documents for the Project
- How to Describe a Hardware Circuit
Important Dates and Deadlines (2017)
- Deadline Assignment 1: September 4th, at 13:15.
- Find classmates that you would like to do the project with: September 5th to 8th.
- Deadline for the registration in the course: September 11th.
- Period to register the project groups: September 11th to September 13th.
- Deadline Assignment 2: September 13th, at 8:15.
- Deadline Laboratories 1 and 2: September 13th. IMP: Required to participate in the project.
- List of definitive project groups: September 14th. IMP: Check which is your group, meet your group mates and book the first meeting with the supervisor.
- First meeting of the project group with the supervisor: September 15th.
- Second meeting with the supervisor: September 19th or 20th.
- Deadline Assignment 3: September 22th, at 13:15..
- Deadline for the final version of the Requirements Specification: September 22nd.
- Time Report 1: September 22nd.
- Deadline Laboratories 3 and 4: September 26th.
- Third meeting with the supervisor: September 28th or September 29th.
- Deadline Assignment 4: September 29th, at 10:15.
- Time Report 2: September 29th.
|Final version of the Design Specification and Project Plan||24h before first presentation|
|First Presentation||October 3rd, 4th or 5th|
|First version of the Project Report||October 18th|
|Final version of the Project Report||24h before final presentation|
|Final Presentation||October 27th|
|Time Reports||Every Friday|
Senast uppdaterad: 2017-09-20