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TSIU03 - System Design

Course Description

TSIU03 is an introductory course to circuit design using VHDL. The general description of the course can be found in the Study Plan. The course is intended for bachelor students with no previous knowledge in VHDL. Students of the course are supposed to have previous knowledge in switching theory and it is highly recommended to have studied circuit design before. Master students (specially those that have knowledge in circuit design and programming skills) should preferably apply for the more advanced course Design of Digital Systems (TSTE12). Due to a partial overlap between the content in TSIU03 and TSTE12, it is only allowed to register for one of these courses.

Credits: 8 ECTS

For more information, read the Course Description document.

Registration for the course: Studieportalen.


Mario Garrido: Course responsible
Petter Källström: Labs and Project
Narges Mohammadi: Labs

Course Books

"VHDL for Logic Synthesis", Andrew Rushton. John Wiley & Sons, 2011 (3rd edition). ISBN-13: 978-0470688472. Links: LIU Library, Online Version.

"Digital Design: An Embedded Systems Approach Using VHDL", Peter J. Ashenden. Morgan Kaufmann, 2007. ISBN-13: 978-0123695284. Links: LIU Library, Online Version.


You can download the lectures here. I recommend that you go through the lectures and try to solve the questions again. You can ask any doubt to the teachers.

You can download the laboratories here. The laboratories will be uploaded to the web page before the corresponding laboratory session, so that you can start and work on them whenever you want.

- Important documents for the project: - Templates for the documents of the project: - Other documents:

Important Dates and Deadlines (2018)

Week 37
  • Deadline Assignment 1: September 10th, at 13:15.
  • Find classmates that you would like to do the project with: September 11th to 14th.
Week 38
  • Deadline for the registration in the course: September 17th.
  • Period to register the project groups: September 17th to September 18th.
  • Deadline Laboratories 1 and 2: September 18th. IMP: Required to participate in the project.
  • List of definitive project groups: September 19th. IMP: Check which is your group, meet your group mates and book the first meeting with the supervisor.
  • First meeting of the project group with the supervisor: September 20th or 21st.
  • Deadline Assignment 2: September 21st, at 13:15.
Week 39
  • Second meeting with the supervisor: September 25th or 26th.
  • Deadline for the final version of the Requirements Specification: September 28th.
  • Deadline Assignment 3: September 28th, at 13:15.
  • Time Report 1: September 28th.
Week 40
  • Deadline Laboratories 3 and 4: October 1st at 17:00.
  • Third meeting with the supervisor: October 4th or October 5th.
  • Time Report 2: October 5th.
Week 41
  • Final version of the Design Specification and Project Plan: October 10th.
  • First Presentation: October 11th or 12th.
  • Time Report 3: October 12th.
Week 42
  • Time Report 4: October 19th.
Week 43
  • First version of the Project Report: October 22nd.
  • Final version of the Project Report: October 26th.
  • Time Report 5: October 26th.
Week 44
  • Final Presentation: October 29th or 30th.

Senast uppdaterad: 2018-10-30