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TSEK37 - Analog CMOS Integrerade Kretsar

Analog CMOS Integrated Circuits, 6 HP

Course Information
NEWS:
2016-11-01: The first lecture will be given on 4 November 2016.
2015-10-30: The first lecture will be given on 3 November 2015.
2014-10-08: The first lecture will be given on 4 November 2014.

General


  • Aim:
    This course is intended to give a detailed knowledge and experience in design of advanced VLSI circuits and chips in today's and future nano-scale CMOS technologies. Major VLSI design challenges will be studied, followed by careful treatment of several versatile analog, digital, and mixed analog-digital circuit building blocks frequently utilized in VLSI chips.
  • Course Code:
    TSEK37 Analog CMOS Integrated Circuits/ Analoga CMOS integrerade kretsar, Y4, D4 and IT4, 6 hp
  • Prerequisites:
    TSTE86 Digital Integrated Circuits.
  • Supplementary courses:
    VLSI Design Project, TSEK06, where students follow the entire VLSI design-flow and make 'Real' chips in a standard CMOS process.
  • Organization:
    This course comprises lectures, tutorials, and laboratory exercises. The tutorials support the course by detailed analysis of some problem examples, and the 12 hours laboratory exercises allows students to learn circuit design, simulations, and evaluation techniques utilizing professional CAD tools and standard CMOS process technology models and parameters.
  • Background and motivation:
    Today's and future advanced VLSI chips can comfortably include over one billion of transistors in a single piece of silicon with an area of a few square millimeters! Obviously, these transistors are not just there randomly, but each device is carefully designed and positioned to do its job, and to interact with other devices and circuits which might be in the neighborhood or sometimes in the far end of the chip! Despite 6-7 electrically isolated metal layers available on-chip, it's not so hard to imagine what a nightmare is to lay out these billion of devices and to route all the interconnections between them!
    This might sound cool and challenging enough, but we haven't even scratched the surface yet! It's just the beginning of the story! Even if you have completed the entire layout correctly, still, who knows that the chip will really work? What about all those tough power and performance specifications which must be met in the presence of serious and increasingly large process variations? How do you know that the real chip will operate as you expect. Did you model everything correctly across all process corners? Did you simulate everything correctly? Did you take into account all noise sources? Did you use a correct circuit topology with sufficient robustness against potential noise and signal timing uncertainties? Did you follow all the manufacturing requirements for product reliability and life time? Is that really a high-yield design, where at least over 90% of the chips will work and can be shipped out to customer? ....OR you are just about to fail A Multi-Million Dollar project?
  • Course contents:
    The course will focus on the following topics:
    1- Overview of advanced CMOS process technologies.
    2- Modeling of MOS transistors and passive elements for analog and digital circuits.
    3- Circuit analysis as well as design and simulation strategies required to evaluate analog and digital CMOS integrated circuits. As a representative benchmark, different amplifier stages and other basic circuit building blocks will be studied. The circuit analyses will take into account non-ideal effects such as noise and potential variations in process parameters, terminals voltages, and operating temperature.
    4- On-chip interconnects design and I/O interface circuits. This includes studies on interconnects delay models for high-speed data transmission as well as power and performance analysis of on-chip buses including driver/receiver circuits.
    5- On-chip timing and synchronization techniques, including detailed studies on clock generators, clock distribution networks, and clocking elements such as latches and flip-flops. Also, major clock- and data-recovery circuits such as phase- and delay-locked-loops will be discussed.
    6- Analysis of on-chip power consumption, low power circuit techniques, transistor leakage currents, and leakage current reduction techniques for both active and standby operating modes.
    7- On-chip power delivery and management, including power distribution and power delivery techniques.
    8- Overview of chip manufacturing requirements such as product yield and product reliability, as well as chip testing methodologies.
  • More information for students who are planning their future courses:
    "VLSI" refers to Very Large Scale Integrated circuits (chips that can today include over billions of transistors in a single and small piece of silicon). For example microprocessors in PC's and other computers are VLSI chips. The department of electrical engineering (ISY) provides a world class VLSI education package including 4 courses starting with (i) the introductory course, Digital Integrated Circuits, TSTE86, (ii) the Analog CMOS Integrated Circuits, TSEK37 (this course), and (iii) the 'ultimate' and perhaps the most expensive course in LiTH, "VLSI Chip Design Project course", TSEK06, where students follow the entire VLSI design flow and make "Real" chips in a standard CMOS process. The chips can then be measured in a short course, "Evaluation of an Integrated Circuit", TSEK11.

  • Course literature:
    1. Behzad Razavi, "Design of Analog CMOS Integrated Circuits", 1st Edition McGraw-Hill Higher Education, ISBN 9780071188395 Errata
    2. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital Integrated Circuits", Prentice Hall, Second Edition (International edition), ISBN 0-13-120764-4 (The same book used in the introductory course, TSTE86, Digital Integrated Circuits).
  • Examination:
    TEN1 Written Exam. 4.5 ECTS credits (3p Swedish)
    LAB1 Laboratory work. 1.5 ECTS credits (1p Swedish)
  • www:
    On the current home page, news will be provided as the course progresses -- especially you should keep track on the schedule. The schedule can be found on Timedit and information about each lecture is shown in a table at the bottom of this page.
  • Staff
    • Examiner:
      Atila Alvandpour, Professor
      Electronic Devices, Dept. of Electrical Engineering (ISY)
      Office 229:206, B-building
      Tel: 285818
      E-mail: atila@isy.liu.se
    • Head Teaching Assistant
      Martin Nielsen-Lönn, Ph.D. Student
      Electronic Devices, Department of Electrical Engineering (ISY)
      Office 3D:535, B-huset
      E-mail: martin.nielsen.lonn@liu.se

LABORATORY EXERCISES

There are one laboratory exercise in this course; AnalogLab, which is divided into 3 parts and 3 lab occasions. No registration is required! Carefully prepare the lab! Do not show up un-prepared!!!

Course Labs: The lab manual can be found here.

TUTORIALS

Before each tutorial (as the course proceeds) you will be able to download supplementary material such as answers and hints to exercises that will be treated.

See the link Tutorials in the menu on the right.

OLD EXAMS

Examination 2012-04-13:

Examination 2012-12-22: Examination 2013-03-27: Examination 2014-01-18: Examination 2015-04-10: Examination 2015-08-26: Examination 2016-01-16:

SCHEDULE

  • FÖ = Lecture, LE = Exercise, LA = Lab
Week 44, 2016 Course Element Studentgrp Teacher Local Remark
Fri 4 Nov 15-17 TSEK37 SOC1, COE1 Atila Alvandpour P18 Introduction
 
Week 45
Tue 8 Nov 10-12 TSEK37 SOC1, COE1 Atila Alvandpour R18 Single-ended Amps. (Ch. 3)
Wed 9 nov 8-10 TSEK37 LE SOC1, COE1 Martin Nielsen-Lönn P22 Single-ended Amps.
Thu 10 nov 13-15 TSEK37 SOC1, COE1 Atila Alvandpour R18 Differential Amps. (Ch. 4)
Fri 11 nov 15-17 TSEK37 LE SOC1, COE1 Martin Nielsen-Lönn P18 Differential Amps.
 
Week 46
Tue 15 nov 10-12 TSEK37 SOC1, COE1 Atila Alvandpour P36 Frequency response (Ch. 6)
Thu 17 nov 13-15 TSEK37 SOC1, COE1 Atila Alvandpour P36 Feedback, stability (Ch. 8, 9, 10)
Fri 18 nov 15-17 TSEK37 LE SOC1, COE1 Martin Nielsen-Lönn P18 Frequency Response
 
Week 47, 2016
Tue 22 nov 10-12 TSEK37 SOC1, COE1 Atila Alvandpour R19 Feedback, stability cont. (Ch. 8, 9, 10)
Wed 20 nov 8-10 TSEK37 LE SOC1, COE1 Martin Nielsen-Lönn P22 Feedback, stability and frequency compensation
Thu 24 nov 13-15 TSEK37 SOC1, COE1 Atila Alvandpour P36 Interconnects
Thu 24 nov 17-21 TSEK37 LA SOC1, COE1 Martin Nielsen-Lönn Asgård  
Fri 25 nov 15-17 TSEK37 LE SOC1, COE1 Martin Nielsen-Lönn P18 Interconnects

Informationsansvarig: Atila Alvandpour
Senast uppdaterad: 2016-11-21