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TSEK06 - VLSI konstruktion

A CDIO course for Y4, D4, IT4, COE and SOC
Periods 3 and 4
Credits: 12 HP

  • One of the few courses in the world that teaches the complete design flow from idea to fabricated chip
  • The course has recieved very positive feedback from students that attended the course
  • Highly recommended for students who plan to have a career as VLSI circuit design engineers or researchers

Important Information

Group formation and project selection will take place during the second lecture of the course. If you are unable to attend at that time, you have two options; i) form a group beforehand with fellow students and have them put you on their group list during the selection lecture (make sure that they can give your student ID on the form, and that the group size does not exceed 5 people); or ii) send the head teaching assistant an e-mail and he will try to accomodate you into one of the groups.

Course Description

A comprehensive introduction to design and fabrication of Very Large Scale Integrated (VLSI) circuits in CMOS technology. The course gives an excellent insight into VLSI chip design and high-performance, low-power circuit techniques. The course supports the CDIO project flow and the LIPS project model to promote teamwork and communication skills required by industry to run large and complex design projects.

Course Format

  • 8 lectures support the design projects including project descriptions, project planning, and VLSI circuits and chip design techniques in sub-micron CMOS.
  • 6 X 4 hours labs (a mini-project) introduce the full design flow and CAD tools to be used in the actual projects.
  • Chip design project (the main part of the course): 4-5 students/team design a complete and ready-for-fabrication VLSI chip in a 0.35 µm CMOS process. Each team has the opportunity to select one of many pre-defined design projects on digital, mixed-signal, and/or RF circuits. Past project examples include: processor- and ALU-blocks, digital camera sensors, memories, high-speed I/0, advanced timing circuits, ADCs, DACs, filters, radio transceiver blocks, etc.
  • At the end of the course, the designed circuits will be sent for fabrication to an Austrian CMOS process foundry. The manufactured chips will be available for measurement in a follow-up course, TSEK11 Evaluation of an Integrated Circuit.


  • There are six 4-hour lab occasions where you will go through the complete CAD workflow, from high-level modeling to layout and parasitic extraction, and finally the the assembly of a ready-to-fabricate chip.
  • The labs are solved in groups of 2 students. There are multiple rooms booked so that all students will be fit into each session. There is no prior registration for any occasion, just show up on time and start working.
  • The labs are fully described in the laboratory manual that is available for purchase at Bokakademin (the bookshop in Kårallen, see Literature below).
  • To make it easier for yourselves, come well-prepared to each lab, i.e: solve the preparatory excercises and make sure you have read through the lab thoroughly. Also, try to finish the labs as soon as possible as this will help you with your projects. If you find that you are having trouble finishing the labs during the scheduled time, then you may need to work on your own time as well.


  • Laboratory Manual - TSEK06 VLSI Chip Design Project
    Available at LiU Servicecenter, House A, entrance 19 C, price 94 SEK (number A1493)
  • Project Guide - TSEK06 VLSI Chip Design Project and TSEK11 Evaluation of an IC
  • Jan M. Rabaey, Digital Integrated Circuits,
    Prentice-Hall International Edition, ISBN 0-13-394271-6, 1996
  • Behzad Razavi, Design of Analog CMOS Integrated Circuits,
    McGraw Hill International Edition, ISBN 9780071188395, 2003


  • Completed labs
  • Completed chip design and final project report before the project deadline


Pass or Fail.

Recommended Background Knowledge

Fundamentals of electronics, switching theory, MOS transistors and CMOS technology, radio electronics, digital and analog integrated circuits.


  • Instructor
    Atila Alvandpour, Professor
    Integrated Circuit and Systems, Department of Electrical Engineering (ISY)
    Office 3D:523, B-huset
    Tel: 013-28 58 18
    E-mail: atila@isy.liu.se
  • Head Teaching Assistant
    Martin Nielsen-Lönn, Ph.D. Student
    Integrated Circuits and Systems, Department of Electrical Engineering (ISY)
    Office 3D:535, B-huset
    Tel: 013-28 89 46
    E-mail: martin.nielsen.lonn@liu.se

Available Projects for 2017

Links to the specifications for all of the projects that are available for this year are given below:

A repository of project specifications for earlier years of this course is available here.

Deadlines and Important Dates for 2017

16 Jan. 2017 Course start.
18 Jan. 2017 Project selection. This will be done at the second lecture.
17 Feb. 2017 Deadline for high-level design and simulation report.
24 Mar. 2017 Deadline for transistor level design and simulation report.
19 May 2017 Layout, LVS, DRC and parasitic simulation should be complete. Only slight touch ups and integration changes may remain.
24 May 2017 Tape out. Hard deadline for delivery of chip GDSII file.
26 May 2017 Deadline for final project report.
26 May 2017 Project presentation.

Chip Photos from Previous Years


Here are links to some information and documents that you may find useful when doing your project:

Informationsansvarig: Atila Alvandpour
Senast uppdaterad: 2017-01-17